參數(shù)資料
型號(hào)： DSP56F807PY80E
廠(chǎng)商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 20/60頁(yè)
文件大?。?/td> 522K
代理商： DSP56F807PY80E
56F807 Technical Data Technical Data, Rev. 15
20
Freescale Semiconductor
2.14 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V
±
10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in
Table 3-1
are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
Table 2-19 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
TCK
Input
(Schmitt)
Input, pulled
low internally
Test Clock Input
—This input pin provides a gated clock to synchronize
the test logic and shift serial data to the JTAG/OnCE port. The pin is
connected internally to a pull-down resistor.
1
TMS
Input
(Schmitt)
Input, pulled
high internally
Test Mode Select Input
—This input pin is used to sequence the JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK
and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
1
TDI
Input
(Schmitt)
Input, pulled
high internally
Test Data Input
—This input pin provides a serial input data stream to
the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
1
TDO
Output
Tri-stated
Test Data Output
—This tri-statable output pin provides a serial output
data stream from the JTAG/OnCE port. It is driven in the Shift-IR and
Shift-DR controller states, and changes on the falling edge of TCK.
1
TRST
Input
(Schmitt)
Input, pulled
high internally
Test Reset
—As an input, a low signal on this pin provides a reset signal
to the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted at power-up and whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware
device reset is required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.
Note:
be used in a debugging environment, TRST may be tied to V
SS
through a 1K
resistor.
For normal operation, connect TRST directly to V
SS
. If the design is to
1
DE
Output
Output
Debug Event
—DE provides a low pulse on recognized debug events.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56F807PY80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
DSP56F807PY80E 制造商:Freescale Semiconductor 功能描述:DSP LQFP160 3.6V
DSP56F807VF80 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F807VF80E 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F807VF80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC
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