- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377001 > DSP56F807PY80E (飛思卡爾半導體(中國)有限公司) 16-bit Digital Signal Controllers PDF資料下載
參數(shù)資料
| 型號： | DSP56F807PY80E |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 522K |
| 代理商： | DSP56F807PY80E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F807 Technical Data Technical Data, Rev. 15
Freescale Semiconductor
35
3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1,5
Operating Conditions:
V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control Signals
High Impedance
t
RAZ
—
21
ns
3-12
Minimum RESET Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
t
RA
275,000T
128T
—
—
ns
ns
3-12
RESET Deassertion to First External Address Output
t
RDA
33T
34T
ns
3-12
Edge-sensitive Interrupt Request Width
t
IRW
1.5T
—
ns
3-13
IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine
t
IDM
15T
—
ns
3-14
IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine
t
IG
16T
—
ns
3-14
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State
3
3.
not the minimum required so that the IRQA interrupt is accepted.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
t
IRI
13T
—
ns
3-15
IRQA Width Assertion to Recover from Stop State
4
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
t
IW
2T
—
ns
3-16
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
3-16
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
3-17
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
3-17
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56F807VF80E | 16-bit Digital Signal Controllers |
| DSP56F807 | 16-bit Hybrid Controller(16位混合控制器) |
| DSP56F826BU80 | 16-bit Digital Signal Controllers |
| DSP56F826BU80E | 16-bit Digital Signal Controllers |
| DSP56F826E | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56F807PY80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F807PY80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP160 3.6V |
| DSP56F807VF80 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56F807VF80E | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16 BIT HYBRID CONTROLLER RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56F807VF80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC |
發(fā)布緊急采購，3分鐘左右您將得到回復。