參數(shù)資料
型號(hào)： DSP56F826
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Hybrid Controller(16位混合控制器)
中文描述： 16位混合控制器（16位混合控制器）
文件頁(yè)數(shù)： 35/48頁(yè)
文件大?。?/td> 1011K
代理商： DSP56F826
Synchronous Serial Interface (SSI) Timing
56F826 Technical Data
35
3.10 Synchronous Serial Interface (SSI) Timing
Table 16. SSI Master Mode
1
Switching Characteristics
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
1.
2.
3.
SCSR) and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the
frame sync have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS in the tables and in the figures.
4.
50% duty cycle
5.
bl = bit length; wl = word length
Master mode is internally generated clocks and frame syncs
Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in
Parameter
Symbol
Min
Typ
Max
Units
STCK frequency
fs
10
2
MHz
STCK period
3
t
SCKW
100
—
—
ns
STCK high time
t
SCKH
50
4
—
—
ns
STCK low time
t
SCKL
50
4
—
—
ns
Output clock rise/fall time (STCK, SRCK)
—
4
—
ns
Delay from STCK high to STFS (bl) high - Master
5
t
TFSBHM
0.1
—
0.5
ns
Delay from STCK high to STFS (wl) high - Master
5
t
TFSWHM
0.1
—
0.5
ns
Delay from SRCK high to SRFS (bl) high - Master
5
t
RFSBHM
0.6
—
1.3
ns
Delay from SRCK high to SRFS (wl) high - Master
5
t
RFSWHM
0.6
—
1.3
ns
Delay from STCK high to STFS (bl) low - Master
5
t
TFSBLM
-1.0
—
-0.1
ns
Delay from STCK high to STFS (wl) low - Master
5
t
TFSWLM
-1.0
—
-0.1
ns
Delay from SRCK high to SRFS (bl) low - Master
5
t
RFSBLM
-0.1
—
0
ns
Delay from SRCK high to SRFS (wl) low - Master
5
t
RFSWLM
-0.1
—
0
ns
STCK high to STXD enable from high impedance - Master
t
TXEM
20
—
22
ns
STCK high to STXD valid - Master
t
TXVM
24
—
26
ns
STCK high to STXD not valid - Master
t
TXNVM
0.1
—
0.2
ns
STCK high to STXD high impedance - Master
t
TXHIM
24
—
25.5
ns
SRXD Setup time before SRCK low - Master
t
SM
4
—
—
ns
SRXD Hold time after SRCK low - Master
t
HM
4
—
—
ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master
t
TSM
4
—
—
SRXD Hold time after STCK low - Master
t
THM
4
—
—
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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