參數(shù)資料
型號(hào): DSP56F827E
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-bit Digital Signal Controllers
中文描述: 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù): 43/60頁(yè)
文件大?。?/td> 811K
代理商: DSP56F827E
Synchronous Serial Interface (SSI) Timing
56F827 Technical Data, Rev. 12
Freescale Semiconductor
43
1.
2.
3.
4.
Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only
connected to it at sampling time. (1pf)
Figure 3-24 Equivalent Analog Input Circuit
3.11 Synchronous Serial Interface (SSI) Timing
2.
Measured in 10-90% range.
3.
LSB = Least Significant Bit.
4.
Guaranteed by characterization.
5. t
AIC
= 1/
f
ADIC
Table 3-14 SSI Master Mode
1
Switching Characteristics
Operating Conditions:
V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
< 50pF, f
op
= 80MHz
Parameter
Symbol
Min
Typ
Max
Units
STCK frequency
fs
10
2
MHz
STCK period
3
t
SCKW
100
ns
STCK high time
t
SCKH
50
4
ns
STCK low time
t
SCKL
50
4
ns
Output clock rise/fall time
4
ns
Delay from STCK high to STFS (bl) high - Master
5
t
TFSBHM
0.1
0.5
ns
Delay from STCK high to STFS (wl) high - Master
5
t
TFSWHM
0.1
0.5
ns
Delay from SRCK high to SRFS (bl) high - Master
5
t
RFSBHM
0.6
1.3
ns
Delay from SRCK high to SRFS (wl) high - Master
5
t
RFSWHM
0.6
1.3
ns
Delay from STCK high to STFS (bl) low - Master
5
t
TFSBLM
-1.0
-0.1
ns
1
2
3
4
ADC analog input
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