參數(shù)資料
型號(hào)： DSPA56721AG
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
中文描述： SymphonyTM DSP56720 / DSP56721多核音頻處理器
文件頁(yè)數(shù)： 36/54頁(yè)
文件大?。?/td> 671K
代理商： DSPA56721AG
Symphony
TM
DSP56720 / DSP56721 Multi-Core Audio Processors, Rev.1
Freescale Semiconductor
36
320
Write data strobe assertion width
7
HACK write assertion width
Write data strobe deassertion width
7
HACK write deassertion width
after ICR, CVR and “Last Data Register” writes
4
–
13.2
–
ns
321
2
×
T
C
+ 6.6
16.6
–
ns
after IVR writes, or
after TXH:TXM writes (with HBE=0), or
after TXL:TXM writes (with HBE=1)
–
16.5
–
322
HAS assertion width
HAS deassertion to data strobe assertion
8
Host data input setup time before write data strobe deassertion
7
Host data input setup time before HACK write deassertion
Host data input hold time after write data strobe deassertion
7
Host data input hold time after HACK write deassertion
Read data strobe assertion to output data active from high impedance
3
HACK read assertion to output data active from high impedance
Read data strobe assertion to output data valid
3
HACK read assertion to output data valid
Read data strobe deassertion to output data high impedance
3
HACK read deassertion to output data high impedance
Output data hold time after read data strobe deassertion
3
Output data hold time after HACK read deassertion
HCS assertion to read data strobe deassertion
3
HCS assertion to write data strobe deassertion
7
–
9.9
–
ns
323
–
0.0
–
ns
324
–
9.9
–
ns
325
–
3.3
–
ns
326
–
3.3
–
ns
327
–
–
24.2
ns
328
–
–
9.9
ns
329
–
3.3
–
ns
330
T
C
+ 9.9
14.9
–
ns
331
–
9.9
–
ns
332
HCS assertion to output data valid
HCS hold time after data strobe deassertion
8
–
–
19.1
ns
333
–
0.0
–
ns
334
Address (AD7–AD0) setup time before HAS deassertion (HMUX=1)
–
4.7
–
ns
335
Address (AD7–AD0) hold time after HAS deassertion (HMUX=1)
–
3.3
–
ns
336
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W setup time before data
strobe assertion
8
Read
–
0
–
ns
Write
–
4.7
–
337
A10–A8 (HMUX=1), A2–A0 (HMUX=0), HR/W hold time after data strobe
deassertion
8
–
3.3
–
ns
338
Delay from read data strobe deassertion to
host request assertion for “Last Data Register” read
3, 4, 9
T
C
5.0
–
ns
Table 18. HDI24 Timing Parameters (Continued)
No.
Characteristics
2
Expression
200 MHz
Unit
Min
Max
相關(guān)PDF資料
PDF描述
DSPB56720AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AF SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPB56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSP56800ERM 16-bit Digital Signal Controllers
DSP56800E Digitial Signal Controller
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