參數(shù)資料
型號(hào)： DSPB56371AF180
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/68頁(yè)
文件大?。?/td> 0K
描述： IC DSP 24BIT 180MHZ 80-LQFP
標(biāo)準(zhǔn)包裝： 90
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時(shí)鐘速率： 180MHz
非易失內(nèi)存： ROM（384 kB）
芯片上RAM： 264kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.25V
工作溫度： -40°C ~ 115°C
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
DSP56371 Data Sheet, Rev. 4.1
Signal/Connection Descriptions
Freescale Semiconductor
14
3.3
Ground
3.4
SCAN
3.5
Clock and PLL
Table 3. Grounds
Ground Name
Description
PLLA_GND(1)
PLLP_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
PLLD_GND(1)
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
CORE_GND (4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user must
provide adequate external decoupling capacitors.
IO_GND (5)
SHI, ESAI, ESAI_1, DAX and Timer I/O Ground—IO_GND is an isolated ground for the SHI, ESAI,
ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
Table 4. SCAN Signals
Signal
Name
Type
State
During
Reset
Signal Description
SCAN
Input
SCAN—Manufacturing test pin. This pin should be pulled low.
Internal Pull down resistor.
Table 5. Clock and PLL Signals
Signal
Name
Type
State
during
Reset
Signal Description
EXTAL
Input
External Clock Input—An external clock source must be connected to EXTAL in
order to supply the clock to the internal clock generator and PLL.
This input is 5 V tolerant.
PINIT/NMI
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is
a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
Internal Pull up resistor.
This input is 5 V tolerant.
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參數(shù)描述
DSPB56371AF180 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC
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