參數(shù)資料
型號: DSPB56374AE
廠商: Freescale Semiconductor
文件頁數(shù): 3/64頁
文件大?。?/td> 0K
描述: IC DSP 24BIT 150MHZ 52-LQFP
標準包裝: 160
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機接口,I²C,SAI,SPI
時鐘速率: 150MHz
非易失內(nèi)存: ROM(84 kB)
芯片上RAM: 54kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.25V
工作溫度: -40°C ~ 110°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應商設備封裝: 52-LQFP(10x10)
包裝: 托盤
Signal Groupings
DSP56374 Data Sheet, Rev. 4.2
Freescale Semiconductor
11
MOSI
Input or output
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI
is the master data output line. The MOSI signal is used in conjunction with
the MISO signal for transmitting and receiving serial data. MOSI is the slave
data input line when the SPI is configured as a slave. This signal is a
Schmitt-trigger input when configured for the SPI Slave mode.
HA0
Input
I2C Slave Address 0—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for I2C slave mode, the HA0
signal is used to form the slave device address. HA0 is ignored when
configured for the I2C master mode.
This signal is tri-stated during hardware, software, and individual reset.
Thus, there is no need for an external pull-up in this state.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
SS
Input
Ignored Input SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the
SPI master mode, this signal should be kept de-asserted (pulled high). If it
is asserted while configured as SPI master, a bus error condition is flagged.
If SS is de-asserted, the SHI ignores SCK clocks and keeps the MISO
output signal in the high-impedance state.
HA2
Input
I2C Slave Address 2—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for the I2C Slave mode, the
HA2 signal is used to form the slave device address. HA2 is ignored in the
I2C master mode.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
HREQ
PH4
Input or Output
Input, output, or
disconnected
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when configured for
the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the
SHI is ready for the next data word transfer and de-asserted at the first clock
pulse of the new data word transfer. When configured for the master mode,
HREQ is an input. When asserted by the external slave device, it will trigger
the start of the data word transfer by the master. After finishing the data word
transfer, the master will await the next assertion of HREQ to proceed to the
next transfer. This pin can also be programmed as GPIO.
Port H4—When HREQ is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
This pin has an internal pull up resistor.
This input is 5 V tolerant.
Table 9. Serial Host Interface Signals (continued)
Signal
Name
Signal Type
State during
Reset
Signal Description
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