Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5 Freescale Semicon" />
參數(shù)資料
型號: DSPB56721CAF
廠商: Freescale Semiconductor
文件頁數(shù): 30/54頁
文件大?。?/td> 0K
描述: DSP 24BIT AUD 200MHZ 80-LQFP
標準包裝: 90
系列: DSP56K/Symphony
類型: 音頻處理器
接口: 主機接口,I²C,SAI,SPI
時鐘速率: 200MHz
非易失內(nèi)存: 外部
芯片上RAM: 744kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 1.00V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
Symphony DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5
Freescale Semiconductor
36
320
Write data strobe assertion width
7
HACK write assertion width
—13.2
ns
321
Write data strobe deassertion width
7
HACK write deassertion width
after ICR, CVR and “Last Data Register” writes
4
2
× TC + 6.6
16.6
ns
after IVR writes, or
after TXH:TXM writes (with HBE=0), or
after TXL:TXM writes (with HBE=1)
—16.5
322
HAS assertion width
9.9
ns
323
HAS deassertion to data strobe assertion
8
—0.0
ns
324
Host data input setup time before write data strobe deassertion
7
Host data input setup time before HACK write deassertion
—9.9
ns
325
Host data input hold time after write data strobe deassertion
7
Host data input hold time after HACK write deassertion
—3.3
ns
326
Read data strobe assertion to output data active from high impedance
3
HACK read assertion to output data active from high impedance
—5.9
ns
327
Read data strobe assertion to output data valid
3
HACK read assertion to output data valid
29.6
ns
328
Read data strobe deassertion to output data high impedance
3
HACK read deassertion to output data high impedance
——
9.9
ns
329
Output data hold time after read data strobe deassertion
3
Output data hold time after HACK read deassertion
—3.3
ns
330
HCS assertion to read data strobe deassertion
3
TC + 9.9
14.9
ns
331
HCS assertion to write data strobe deassertion
7
—9.9
ns
332
HCS assertion to output data valid
19.1
ns
333
HCS hold time after data strobe deassertion
8
—0.0
ns
334
Address (AD7—AD0) setup time before HAS deassertion (HMUX=1)
4.7
ns
335
Address (AD7—AD0) hold time after HAS deassertion (HMUX=1)
3.3
ns
336
A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W setup time before data
strobe assertion
8
Read
—0
ns
Write
—4.7
337
A10—A8 (HMUX=1), A2—A0 (HMUX=0), HR/W hold time after data
strobe deassertion
8
—3.3
ns
338
Delay from read data strobe deassertion to
host request assertion for “Last Data Register” read
3, 4, 9
TC
5.0
ns
Table 15. HDI24 Timing Parameters (Continued)
No.
Characteristics
2
Expression
200 MHz
Unit
Min
Max
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DSPB56721CAG 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24-BIT 200MHz RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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DSPB56724CAG 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Symphony? DSP56724/DSP56725 Multi-Core Audio Processors
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