參數(shù)資料
型號(hào): DSPIC30F2020-30I/MM
廠商: Microchip Technology
文件頁(yè)數(shù): 54/66頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 28QFN
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
特色產(chǎn)品: SMPS & Digital Power Conversion Solutions
標(biāo)準(zhǔn)包裝: 61
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲(chǔ)器容量: 12KB(4K x 24)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁(yè)面: 650 (CN2011-ZH PDF)
配用: DM300023-ND - KIT DEMO DSPICDEM SMPS BUCK
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
dsPIC30F Flash Programming Specification
DS70102K-page 58
2010 Microchip Technology Inc.
13.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 13-1:
AC/DC CHARACTERISTICS
Standard Operating Conditions
(unless otherwise stated)
Operating Temperature: 25
° C is recommended
Param.
No.
Sym
Characteristic
Min
Max
Units
Conditions
D110
VIHH
High Programming Voltage on MCLR/VPP
9.00
13.25
V
D112
IPP
Programming Current on MCLR/VPP
—300
μA—
D113
IDDP
Supply Current during programming
30
mA
Row Erase
Program
memory
30
mA
Row Erase
Data EEPROM
30
mA
Bulk Erase
D001
VDD
Supply voltage
2.5
5.5
V
D002
VDDBULK Supply voltage for Bulk Erase
programming
4.5
5.5
V
D031
VIL
Input Low Voltage
VSS
0.2 VSS
V—
D041
VIH
Input High Voltage
0.8 VDD
VDD
V—
D080
VOL
Output Low Voltage
0.6
V
IOL = 8.5 mA
D090
VOH
Output High Voltage
VDD - 0.7
V
IOH = -3.0 mA
D012
CIO
Capacitive Loading on I/O Pin (PGD)
50
pF
To meet AC
specifications
P1
TSCLK
Serial Clock (PGC) period
50
ns
ICSP mode
1—
μs
Enhanced
ICSP mode
P1a
TSCLKL
Serial Clock (PGC) low time
20
ns
ICSP mode
400
ns
Enhanced
ICSP mode
P1b
TSCLKH
Serial Clock (PGC) high time
20
ns
ICSP mode
400
ns
Enhanced
ICSP mode
P2
TSET1
Input Data Setup Timer to PGC
15
ns
P3
THLD1
Input Data Hold Time from PGC
15
ns
P4
TDLY1
Delay between 4-bit command and
command operand
20
ns
P4a
TDLY1a
Delay between 4-bit command operand
and next 4-bit command
20
ns
P5
TDLY2
Delay between last PGC
↓of command to
first PGC
↑ of VISI output
20
ns
P6
TSET2VDD
↑ setup time to MCLR/VPP
100
ns
P7
THLD2
Input data hold time from MCLR/VPP
2—
μs
ICSP mode
5
ms
Enhanced
ICSP mode
P8
TDLY3
Delay between last PGC
↓ of command
word to PGD driven
↑ by programming
executive
20
μs—
P9a
TDLY4
Programming Executive Command
processing time
10
μs—
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