參數(shù)資料
型號(hào): DSPIC30F3013-30I/ML
廠商: Microchip Technology
文件頁數(shù): 88/161頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 24K 44QFN
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 45
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 20
程序存儲(chǔ)器容量: 24KB(8K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱: DSPIC30F301330IML
2011 Microchip Technology Inc.
DS39932D-page 207
PIC18F46J11 FAMILY
13.5.1
USING TIMER1 AS A
CLOCK SOURCE
The Timer1 oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode; both the CPU and
peripherals are clocked from the Timer1 oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
.
Whenever the Timer1 oscillator is providing the clock
source, the Timer1 system clock status flag, T1RUN
(TCLKCON<4>), is set. This can be used to determine
the controller’s current clocking mode. It can also
indicate the clock source currently being used by the
Fail-Safe Clock Monitor. If the Clock Monitor is enabled
and the Timer1 oscillator fails while providing the clock,
polling the T1RUN bit will indicate whether the clock is
being provided by the Timer1 oscillator or another
source.
13.5.2
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when
the oscillator is configured for extremely low power
mode (LPT1OSC = 0).
The oscillator circuit, displayed in Figure 13-2, should
be located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the
oscillator (such as the ECCP1 pin in Output Compare
or PWM mode, or the primary oscillator using the
OSC2 pin), a grounded guard ring around the oscillator
circuit, as displayed in Figure 13-3, may be helpful
when used on a single-sided PCB or in addition to a
ground plane.
FIGURE 13-3:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
In the low drive level mode, LPT1OSC = 0, it is critical
that RC2 I/O pin signals be kept away from the oscillator
circuit. Configuring RC2 as a digital output, and toggling
it, can potentially disturb the oscillator circuit, even with
relatively good PCB layout. If possible, it is recom-
mended to either leave RC2 unused, or use it as an input
pin with a slew rate limited signal source. If RC2 must be
used as a digital output, it may be necessary to use the
higher drive level oscillator mode (LPT1OSC = 1) with
many PCB layouts. Even in the higher drive level mode,
careful layout procedures should still be followed when
designing the oscillator circuit.
In addition to dV/dt induced noise considerations, it is
also important to ensure that the circuit board is clean.
Even a very small amount of conductive soldering flux
residue can cause PCB leakage currents, which can
overwhelm the oscillator circuit.
13.6
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note:
Not drawn to scale.
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