參數(shù)資料
型號(hào): DSPIC30F3014-30I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 139/153頁(yè)
文件大小: 0K
描述: IC DSPIC MCU/DSP 24K 40DIP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 10
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 30 MIP
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲(chǔ)器容量: 24KB(8K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 651 (CN2011-ZH PDF)
配用: AC30F003-ND - MODULE SOCKET DSPIC30F 40DIP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
其它名稱: DSPIC30F301430/P
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dsPIC30F3014/4013
DS70138G-page 86
2010 Microchip Technology Inc.
13.2
Simple Output Compare Match
Mode
When control bits, OCM<2:0> (OCxCON<2:0>) = 001,
010
or 011, the selected output compare channel is
configured for one of three simple Output Compare
Match modes:
Compare forces I/O pin low
Compare forces I/O pin high
Compare toggles I/O pin
The OCxR register is used in these modes. The OCxR
register is loaded with a value and is compared to the
selected incrementing timer count. When a compare
occurs, one of these Compare Match modes occurs. If
the counter resets to zero before reaching the value in
OCxR, the state of the OCx pin remains unchanged.
13.3
Dual Output Compare Match Mode
When control bits, OCM<2:0> (OCxCON<2:0>) = 100
or 101, the selected output compare channel is config-
ured for one of two Dual Output Compare modes,
which are:
Single Output Pulse mode
Continuous Output Pulse mode
13.3.1
SINGLE PULSE MODE
For the user to configure the module for the generation
of a single output pulse, the following steps are
required (assuming timer is off):
Determine instruction cycle time, TCY.
Calculate desired pulse width value based on TCY.
Calculate time to Start pulse from timer start value
of 0x0000.
Write pulse-width start and stop times into OCxR
and OCxRS Compare registers (x denotes
channel 1, 2, ...,N).
Set Timer Period register to value equal to or
greater than value in OCxRS Compare register.
Set OCM<2:0> = 100.
Enable timer, TON (TxCON<15>) = 1.
To initiate another single pulse, issue another write to
set OCM<2:0> = 100.
13.3.2
CONTINUOUS PULSE MODE
For the user to configure the module for the generation
of a continuous stream of output pulses, the following
steps are required:
Determine instruction cycle time, TCY.
Calculate desired pulse value based on TCY.
Calculate timer to Start pulse width from timer
start value of 0x0000.
Write pulse-width Start and Stop times into OCxR
and OCxRS (x denotes channel 1, 2, ...,N)
Compare registers, respectively.
Set Timer Period register to value equal to or
greater than value in OCxRS Compare register.
Set OCM<2:0> = 101.
Enable timer, TON (TxCON<15>) = 1.
13.4
Simple PWM Mode
When control bits, OCM<2:0> (OCxCON<2:0>) = 110
or 111, the selected output compare channel is config-
ured for the PWM mode of operation. When configured
for the PWM mode of operation, OCxR is the main latch
(read-only) and OCxRS is the secondary latch. This
enables glitchless PWM transitions.
The user must perform the following steps in order to
configure the output compare module for PWM
operation:
1.
Set the PWM period by writing to the appropriate
Period register.
2.
Set the PWM duty cycle by writing to the OCxRS
register.
3.
Configure the output compare module for PWM
operation.
4.
Set the TMRx prescale value and enable the
timer, TON (TxCON<15>) = 1.
13.4.1
INPUT PIN FAULT PROTECTION
FOR PWM
When control bits, OCM<2:0> (OCxCON<2:0>) = 111,
the selected output compare channel is again config-
ured for the PWM mode of operation with the additional
feature of input Fault protection. While in this mode, if
a logic ‘0’ is detected on the OCFA/B pin, the respective
PWM output pin is placed in the high-impedance input
state. The OCFLT bit (OCxCON<4>) indicates whether
a Fault condition has occurred. This state is maintained
until both of the following events have occurred:
The external Fault condition has been removed.
The PWM mode has been re-enabled by writing
to the appropriate control bits.
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