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參數(shù)資料
| 型號(hào)： | DSPIC30F3014-30I/P |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 18/153頁 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 24K 40DIP |
| 產(chǎn)品培訓(xùn)模塊： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 標(biāo)準(zhǔn)包裝： | 10 |
| 系列： | dsPIC™ 30F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 30 MIP |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 30 |
| 程序存儲(chǔ)器容量： | 24KB（8K x 24） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 651 (CN2011-ZH PDF) |
| 配用： | AC30F003-ND - MODULE SOCKET DSPIC30F 40DIP DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL |
| 其它名稱： | DSPIC30F301430/P |
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dsPIC30F3014/4013
DS70138G-page 114
2010 Microchip Technology Inc.
17.4
Message Reception
17.4.1
RECEIVE BUFFERS
The CAN bus module has 3 receive buffers. However,
one of the receive buffers is always committed to mon-
itoring the bus for incoming messages. This buffer is
called the Message Assembly Buffer (MAB). So there
are 2 receive buffers visible, denoted as RXB0 and
RXB1, that can essentially instantaneously receive a
complete message from the protocol engine.
All messages are assembled by the MAB and are trans-
ferred to the RXBn buffers only if the acceptance filter
criterion are met. When a message is received, the
RXnIF flag (CiINRF<0> or CiINRF<1>) is set. This bit
can only be set by the module when a message is
received. The bit is cleared by the CPU when it has com-
pleted processing the message in the buffer. If the
RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt
is generated when a message is received.
RXF0 and RXF1 filters with RXM0 mask are associated
with RXB0. The filters RXF2, RXF3, RXF4 and RXF5,
and the mask RXM1 are associated with RXB1.
17.4.2
MESSAGE ACCEPTANCE FILTERS
The message acceptance filters and masks are used to
determine if a message in the message assembly buf-
fer should be loaded into either of the receive buffers.
Once a valid message has been received into the Mes-
sage Assembly Buffer (MAB), the identifier fields of the
message are compared to the filter values. If there is a
match, that message is loaded into the appropriate
receive buffer.
The acceptance filter looks at incoming messages for
the RXIDE bit (CiRXnSID<0>) to determine how to
compare the identifiers. If the RXIDE bit is clear, the
message is a standard frame and only filters with the
EXIDE bit (CiRXFnSID<0>) clear are compared. If the
RXIDE bit is set, the message is an extended frame
and only filters with the EXIDE bit set are compared.
17.4.3
MESSAGE ACCEPTANCE FILTER
MASKS
The mask bits essentially determine which bits to apply
the filter to. If any mask bit is set to a zero, that bit is
automatically accepted regardless of the filter bit.
There are two programmable acceptance filter masks
associated with the receive buffers, one for each buffer.
17.4.4
RECEIVE OVERRUN
An overrun condition occurs when the Message
Assembly Buffer (MAB) has assembled a valid
received message, the message is accepted through
the acceptance filters, and when the receive buffer
associated with the filter has not been designated as
clear of the previous message.
The overrun error flag, RXnOVR (CiINTF<15> or
CiINTF<14>), and the ERRIF bit (CiINTF<5>) are set
and the message in the MAB is discarded.
If the DBEN bit is clear, RXB1 and RXB0 operate inde-
pendently. When this is the case, a message intended
for RXB0 is not diverted into RXB1 if RXB0 contains an
unread message, and the RX0OVR bit is set.
If the DBEN bit is set, the overrun for RXB0 is handled
differently. If a valid message is received for RXB0 and
RXFUL = 1
it
indicates
that
RXB0
is
full
and
RXFUL = 0 indicates that RXB1 is empty, the message
for RXB0 is loaded into RXB1. An overrun error is not
generated for RXB0. If a valid message is received for
RXB0 and RXFUL = 1, indicates that both RXB0 and
RXB1 are full, the message is lost and an overrun is
indicated for RXB1.
17.4.5
RECEIVE ERRORS
The CAN module detects the following receive errors:
Cyclic Redundancy Check (CRC) error
Bit Stuffing error
Invalid Message Receive Error
The receive error counter is incremented by one in
case one of these errors occur. The RXWAR bit
(CiINTF<9>) indicates that the receive error counter
has reached the CPU warning limit of 96 and an
interrupt is generated.
17.4.6
RECEIVE INTERRUPTS
Receive interrupts can be divided into 3 major groups,
each including various conditions that generate
interrupts:
Receive Interrupt:
A message has been successfully received and
loaded into one of the receive buffers. This inter-
rupt is activated immediately after receiving the
End-of-Frame (EOF) field. Reading the RXnIF flag
indicates
which
receive
buffer
caused
the
interrupt.
Wake-up Interrupt:
The CAN module has woken up from Disable
mode or the device has woken up from Sleep
mode.
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