參數(shù)資料
型號(hào)： DSPIC30F5011-20I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 28/220頁(yè)
文件大小： 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓(xùn)模塊： Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
標(biāo)準(zhǔn)包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 20 MIPS
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： AC'97，欠壓檢測(cè)/復(fù)位，I²S，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲(chǔ)器容量： 66KB（22K x 24）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤(pán)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
其它名稱： DSPIC30F5011-20I/PTG
DSPIC30F501120/PT-ND
DSPIC30F501120IPT
DSPIC30F501120IPT-ND
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2011 Microchip Technology Inc.
DS70116J-page 123
dsPIC30F5011/5013
18.3.14
BUFFER LENGTH CONTROL
The amount of data that is buffered between interrupts
is determined by the buffer length (BLEN<1:0>) control
bits in the DCICON1 SFR. The size of the transmit and
receive buffers may be varied from 1 to 4 data words
using the BLEN control bits. The BLEN control bits are
compared to the current value of the DCI buffer control
unit address counter. When the 2 LSbs of the DCI
address counter match the BLEN<1:0> value, the buf-
fer control unit will be reset to ‘0’. In addition, the con-
tents of the receive shadow registers are transferred to
the receive buffer registers and the contents of the
transmit buffer registers are transferred to the transmit
shadow registers.
18.3.15
BUFFER ALIGNMENT WITH DATA
FRAMES
There is no direct coupling between the position of the
AGU address pointer and the data frame boundaries.
This means that there will be an implied assignment of
each transmit and receive buffer that is a function of the
BLEN control bits and the number of enabled data slots
via the TSE and RSE control bits.
As an example, assume that a 4-word data frame is
chosen and that we want to transmit on all four time
slots in the frame. This configuration would be estab-
lished by setting the TSE0, TSE1, TSE2 and TSE3
control bits in the TSCON SFR. With this module setup,
the TXBUF0 register would be naturally assigned to
slot #0, the TXBUF1 register would be naturally
assigned to slot #1, and so on.
18.3.16
TRANSMIT STATUS BITS
There are two transmit status bits in the DCISTAT SFR.
The TMPTY bit is set when the contents of the transmit
buffer registers are transferred to the transmit shadow
registers. The TMPTY bit may be polled in software to
determine when the transmit buffer registers may be
written. The TMPTY bit is cleared automatically by the
hardware when a write to one of the four transmit
buffers occurs.
The TUNF bit is read-only and indicates that a transmit
underflow has occurred for at least one of the transmit
buffer registers that is in use. The TUNF bit is set at the
time the transmit buffer registers are transferred to the
transmit shadow registers. The TUNF Status bit is
cleared automatically when the buffer register that
underflowed is written by the CPU.
18.3.17
RECEIVE STATUS BITS
There are two receive status bits in the DCISTAT SFR.
The RFUL Status bit is read-only and indicates that
new data is available in the receive buffers. The RFUL
bit is cleared automatically when all receive buffers in
use have been read by the CPU.
The ROV Status bit is read-only and indicates that a
receive overflow has occurred for at least one of the
receive buffer locations. A receive overflow occurs
when the buffer location is not read by the CPU before
new data is transferred from the shadow registers. The
ROV Status bit is cleared automatically when the buffer
register that caused the overflow is read by the CPU.
When a receive overflow occurs for a specific buffer
location, the old contents of the buffer are overwritten.
Note:
When more than four time slots are active
within a data frame, the user code must
keep track of which time slots are to be
read/written at each interrupt. In some
cases, the alignment between transmit/
receive buffers and their respective slot
assignments could be lost. Examples of
such cases include an emulation break-
point or a hardware trap. In these situa-
tions, the user should poll the SLOT status
bits to determine what data should be
loaded into the buffer registers to
resynchronize the software with the DCI
module.
Note:
The transmit status bits only indicate sta-
tus for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
Note:
The receive status bits only indicate status
for buffer locations that are used by the
module. If the buffer length is set to less
than four words, for example, the unused
buffer locations will not affect the transmit
status bits.
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