參數(shù)資料
型號： DSPIC30F5015-30I/PT
廠商： Microchip Technology
文件頁數(shù)： 3/129頁
文件大?。?/td> 0K
描述： IC DSPIC MCU/DSP 66K 64TQFP
產(chǎn)品培訓模塊： dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標準包裝： 160
系列： dsPIC™ 30F
核心處理器： dsPIC
芯體尺寸： 16-位
速度： 30 MIP
連通性： CAN，I²C，SPI，UART/USART
外圍設備： 高級欠壓探測/復位，電機控制 PWM，QEI，POR，PWM，WDT
輸入/輸出數(shù)： 52
程序存儲器容量： 66KB（22K x 24）
程序存儲器類型： 閃存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
數(shù)據(jù)轉換器： A/D 16x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 651 (CN2011-ZH PDF)
配用： XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名稱： DSPIC30F501530IPT
dsPIC30F5015/5016
DS70149D-page 100
2008 Microchip Technology Inc.
15.6
Complementary PWM Operation
In the Complementary mode of operation, each pair of
PWM outputs is obtained by a complementary PWM
signal. A dead time may be optionally inserted during
device switching, when both outputs are inactive for a
short period (Refer to Section 15.7 “Dead-Time
In Complementary mode, the duty cycle comparison
units are assigned to the PWM outputs as follows:
PDC1 register controls PWM1H/PWM1L outputs
PDC2 register controls PWM2H/PWM2L outputs
PDC3 register controls PWM3H/PWM3L outputs
PDC4 register controls PWM4H/PWM4L outputs
The Complementary mode is selected for each PWM
I/O pin pair by clearing the appropriate PMODx bit in the
PWMCON1 SFR. The PWM I/O pins are set to
Complementary mode by default upon a device Reset.
15.7
Dead-Time Generators
Dead-time generation may be provided when any of the
PWM I/O pin pairs are operating in the Complementary
Output mode. The PWM outputs use Push-Pull drive
circuits. Due to the inability of the power output devices
to switch instantaneously, some amount of time must be
provided between the turn off event of one PWM output
in a complementary pair and the turn on event of the
other transistor.
The PWM module allows two different dead times to be
programmed. These two dead times may be used in
one of two methods described below to increase user
flexibility:
The PWM output signals can be optimized for
different turn off times in the high side and low
side transistors in a complementary pair of
transistors. The first dead time is inserted
between the turn off event of the lower transistor
of the complementary pair and the turn on event
of the upper transistor. The second dead time is
inserted between the turn off event of the upper
transistor and the turn on event of the lower
transistor.
The two dead times can be assigned to individual
PWM I/O pin pairs. This operating mode allows
the PWM module to drive different transistor/load
combinations with each complementary PWM I/O
pin pair.
15.7.1
DEAD-TIME GENERATORS
Each complementary output pair for the PWM module
has a 6-bit down counter that is used to produce the
dead-time insertion. As shown in Figure 15-4, each
dead-time unit has a rising and falling edge detector
connected to the duty cycle comparison output.
15.7.2
DEAD-TIME ASSIGNMENT
The DTCON2 SFR contains control bits that allow the
dead times to be assigned to each of the
complementary outputs. Table 15-1 summarizes the
function of each dead-time selection control bit.
TABLE 15-1:
DEAD-TIME SELECTION BITS
15.7.3
DEAD-TIME RANGES
The amount of dead time provided by each dead-time
unit is selected by specifying the input clock prescaler
value and a 6-bit unsigned value. The amount of dead
time provided by each unit may be set independently.
Four input clock prescaler selections have been
provided to allow a suitable range of dead times, based
on the device operating frequency. The clock prescaler
option may be selected independently for each of the
two dead-time values. The dead-time clock prescaler
values are selected using the DTAPS<1:0> and
DTBPS<1:0> control bits in the DTCON1 SFR. One of
four clock prescaler options (TCY, 2 TCY, 4 TCY or 8 TCY)
may be selected for each of the dead-time values.
After the prescaler values are selected, the dead time
for each unit is adjusted by loading two 6-bit unsigned
values into the DTCON1 SFR.
The dead-time unit prescalers are cleared on the
following events:
On a load of the down timer due to a duty cycle
comparison edge event.
On a write to the DTCON1 or DTCON2 registers.
On any device Reset.
Bit
Function
DTS1A
Selects PWM1L/PWM1H active edge dead time.
DTS1I
Selects PWM1L/PWM1H inactive edge
dead time.
DTS2A
Selects PWM2L/PWM2H active edge dead time.
DTS2I
Selects PWM2L/PWM2H inactive edge
dead time.
DTS3A
Selects PWM3L/PWM3H active edge dead time.
DTS3I
Selects PWM3L/PWM3H inactive edge
dead time.
DTS4A
Selects PWM4L/PWM4H active edge dead time.
DTS4I
Selects PWM4L/PWM4H inactive edge
dead time.
Note:
The user should not modify the DTCON1
or DTCON2 values while the PWM
module is operating (PTEN = 1).
Unexpected results may occur.
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