參數(shù)資料
型號(hào): DSPIC30F6010-20I/PF
廠商: Microchip Technology
文件頁數(shù): 86/110頁
文件大小: 0K
描述: IC PSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測/復(fù)位,LVD,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 144KB(48K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱: DSPIC30F601020IPF
2006 Microchip Technology Inc.
DS70119E-page 75
dsPIC30F6010
13.0
OUTPUT COMPARE MODULE
This section describes the Output Compare module
and associated operational modes. The features pro-
vided by this module are useful in applications requiring
operational modes such as:
Generation of Variable Width Output Pulses
Power Factor Correction
Figure 13-1 depicts a block diagram of the Output
Compare module.
The key operational features of the Output Compare
module include:
Timer2 and Timer3 Selection mode
Simple Output Compare Match mode
Dual Output Compare Match mode
Simple PWM mode
Output Compare during Sleep and Idle modes
Interrupt on Output Compare/PWM Event
These operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where x =
1,2,3,...,N). The dsPIC30F6010 device has 8 compare
channels.
OCxRS and OCxR in the figure represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the “dsPIC30F Family Reference
Manual” (DS70046).
OCxR
Comparator
Output
Logic
Q
S
R
OCM<2:0>
Output Enable
OCx
Set Flag bit
OCxIF
OCxRS
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
OCFA
OCTSEL
0
1
T2P2_MATCH
TMR2<15:0
TMR3<15:0>
T3P3_MATCH
From General Purpose
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
0
1
Timer Module
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