參數(shù)資料
型號(hào): DSPIC30F6010-20I/PF
廠商: Microchip Technology
文件頁數(shù): 94/110頁
文件大?。?/td> 0K
描述: IC PSPIC MCU/DSP 144K 80TQFP
產(chǎn)品培訓(xùn)模塊: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 30F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 20 MIPS
連通性: CAN,I²C,SPI,UART/USART
外圍設(shè)備: 高級(jí)欠壓探測(cè)/復(fù)位,LVD,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲(chǔ)器容量: 144KB(48K x 24)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: DM300019-ND - BOARD DEMO DSPICDEM 80L STARTER
AC164314-ND - MODULE SKT FOR PM3 80PF
DM300020-ND - BOARD DEV DSPICDEM MC1 MOTORCTRL
其它名稱: DSPIC30F601020IPF
dsPIC30F6010
DS70119E-page 82
2006 Microchip Technology Inc.
14.7.2
TIMER OPERATION DURING CPU
IDLE MODE
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit
timer
will
operate
if
the
QEISIDL
bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
14.8
Quadrature Encoder Interface
Interrupts
The quadrature encoder interface has the ability to
generate an interrupt on occurrence of the following
events:
Interrupt on 16-bit up/down position counter
rollover/underflow
Detection of qualified index pulse, or if CNTERR
bit is set
Timer period match event (overflow/underflow)
Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 Status register.
Enabling an interrupt is accomplished via the respec-
tive Enable bit, QEIIE. The QEIIE bit is located in the
IEC2 Control register.
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