參數(shù)資料
型號: DSPIC33FJ128GP310-I/PF
廠商: Microchip Technology
文件頁數(shù): 27/90頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 128K 100TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲器容量: 128KB(128K x 8)
程序存儲器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 654 (CN2011-ZH PDF)
配用: DM300024-ND - KIT DEMO DSPICDEM 1.1
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA330012-ND - MODULE DSPIC33 100P TO 84QFP
MA330011-ND - MODULE DSPIC33 100P TO 100QFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164323-ND - MODULE SKT FOR 100TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 31
dsPIC33F
8.12
I/O Pins
Some pins for the I/O pin functions are multiplexed with
an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
All I/O port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register determines whether the pin is an input or an
output. The Port Data Latch register provides latched
output data for the I/O pins. The Port register provides
visibility of the logic state of the I/O pins. Reading the
Port register provides the I/O pin logic state, while
writes to the Port register write the data to the Port Data
Latch register.
I/O port pins have latch bits (Port Data Latch register).
This register, when read, yields the contents of the I/O
latch and when written, modifies the contents of the I/O
latch, thus modifying the value driven out on a pin if the
corresponding Data Direction register bit is configured
for output. This can be used in read-modify-write
instructions that allow the user to modify the contents
of the Port Data Latch register, regardless of the status
of the corresponding pins.
The I/O pins have the following features:
Schmitt Trigger input
CMOS output drivers
Weak internal pull-up
All I/O pins configured as digital inputs can accept 5V
signals. This provides a degree of compatibility with
external signals of different voltage levels. However, all
digital outputs and analog pins can only generate
voltage levels up to 3.6V.
The input change notification module gives dsPIC33F
devices the ability to generate interrupt requests to the
processor in response to a change of state on selected
input pins. This module is capable of detecting input
changes of state, even in Sleep mode, when the clocks
are disabled. There are up to 24 external signals (CN0
through CN23) that can be selected (enabled) for
generating an interrupt request on a change of state.
Each of the CN pins also has an optional weak pull-up
feature.
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