參數(shù)資料
型號(hào): DSPIC33FJ128GP310-I/PF
廠商: Microchip Technology
文件頁數(shù): 33/90頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 128K 100TQFP
產(chǎn)品培訓(xùn)模塊: dsPIC33F DMAC
Introduction to dsPIC33F Architecture Part 1
Asynchronous Stimulus
Introduction to dsPIC33F Architecture Part 2
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 90
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,LIN,SPI,UART/USART
外圍設(shè)備: AC'97,欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 128KB(128K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 654 (CN2011-ZH PDF)
配用: DM300024-ND - KIT DEMO DSPICDEM 1.1
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
MA330012-ND - MODULE DSPIC33 100P TO 84QFP
MA330011-ND - MODULE DSPIC33 100P TO 100QFP
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
AC164323-ND - MODULE SKT FOR 100TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
2005 Microchip Technology Inc.
Preliminary
DS70155C-page 37
dsPIC33F
TABLE 9-6:
ROTATE/SHIFT INSTRUCTIONS
TABLE 9-7:
BIT INSTRUCTIONS
Assembly
Syntax
Description
Words
Cycles
ASR
f {,WREG}
Destination = arithmetic right shift f
1
ASR
Ws,Wd
Wd = arithmetic right shift Ws
1
ASR
Wb,#lit4,Wnd
Wnd = arithmetic right shift Wb by lit4
1
ASR
Wb,Wns,Wnd
Wnd = arithmetic right shift Wb by Wns
1
LSR
f {,WREG}
Destination = logical right shift f
1
LSR
Ws,Wd
Wd = logical right shift Ws
1
LSR
Wb,#lit4,Wnd
Wnd = logical right shift Wb by lit4
1
LSR
Wb,Wns,Wnd
Wnd = logical right shift Wb by Wns
1
RLC
f {,WREG}
Destination = rotate left through Carry f
1
RLC
Ws,Wd
Wd = rotate left through Carry Ws
1
RLNC
f {,WREG}
Destination = rotate left (no Carry) f
1
RLNC
Ws,Wd
Wd = rotate left (no Carry) Ws
1
RRC
f {,WREG}
Destination = rotate right through Carry f
1
RRC
Ws,Wd
Wd = rotate right through Carry Ws
1
RRNC
f {,WREG}
Destination = rotate right (no Carry) f
1
RRNC
Ws,Wd
Wd = rotate right (no Carry) Ws
1
SL
f {,WREG}
Destination = left shift f
1
SL
Ws,Wd
Wd = left shift Ws
1
SL
Wb,#lit4,Wnd
Wnd = left shift Wb by lit4
1
SL
Wb,Wns,Wnd
Wnd = left shift Wb by Wns
1
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
Assembly
Syntax
Description
Words
Cycles
BCLR
f,#bit4
Bit clear f
1
BCLR
Ws,#bit4
Bit clear Ws
1
BSET
f,#bit4
Bit set f
1
BSET
Ws,#bit4
Bit set Ws
1
BSW.C
Ws,Wb
Write C bit to Ws<Wb>
1
BSW.Z
Ws,Wb
Write SZ bit to Ws<Wb>
1
BTG
f,#bit4
Bit toggle f
1
BTG
Ws,#bit4
Bit toggle Ws
1
BTST
f,#bit4
Bit test f
1
BTST.C
Ws,#bit4
Bit test Ws to C
1
BTST.Z
Ws,#bit4
Bit test Ws to SZ
1
BTST.C
Ws,Wb
Bit test Ws<Wb> to C
1
BTST.Z
Ws,Wb
Bit test Ws<Wb> to SZ
1
BTSTS
f,#bit4
Bit test f then set f
1
BTSTS.C
Ws,#bit4
Bit test Ws to C then set Ws
1
BTSTS.Z
Ws,#bit4
Bit test Ws to SZ then set Ws
1
FBCL
Ws,Wnd
Find bit change from left (MSb) side
1
FF1L
Ws,Wnd
Find first one from left (MSb) side
1
FF1R
Ws,Wnd
Find first one from right (LSb) side
1
Note:
Bit positions are specified by bit4 (0:15) for word operations.
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