參數(shù)資料
型號: DSPIC33FJ12MC202-I/ML
廠商: Microchip Technology
文件頁數(shù): 127/155頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 28QFN
產品培訓模塊: Asynchronous Stimulus
特色產品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 61
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 6x10b/12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產品目錄頁面: 651 (CN2011-ZH PDF)
配用: AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
73
A/T89C51AC2
4127H–8051–02/08
Watchdog Timer During
Power-down Mode and
Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode, the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power-down mode. When Power-down is exited with
hardware reset, the Watchdog is disabled. Exiting Power-down with an interrupt is sig-
nificantly different. The interrupt shall be held low long enough for the oscillator to
stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started
until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-
rupt service for the interrupt used to exit Power-down.
To ensure that the WDT does not overflow within a few states of exiting powerdown, it is
best to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting
A/T89C51AC2 while in Idle mode, the user should always set up a timer that will period-
ically exit Idle, service the WDT, and re-enter Idle mode.
Register
Table 53. WDTPRG Register
WDTPRG (S:A7h)
Watchdog Timer Duration Programming Register
Reset Value = XXXX X000b
7
6
5
4
3
2
1
0
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
S2
Watchdog Timer Duration selection bit 2
Work in conjunction with bit 1 and bit 0.
1
S1
Watchdog Timer Duration selection bit 1
Work in conjunction with bit 2 and bit 0.
0
S0
Watchdog Timer Duration selection bit 0
Work in conjunction with bit 1 and bit 2.
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