參數(shù)資料
型號: DSPIC33FJ12MC202-I/SO
廠商: Microchip Technology
文件頁數(shù): 74/155頁
文件大?。?/td> 0K
描述: IC DSPIC MCU/DSP 12K 28SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 27
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設(shè)備: 高級欠壓探測/復(fù)位,電機(jī)控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 651 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
2007-2011 Microchip Technology Inc.
DS70265E-page 3
dsPIC33FJ12MC201/202
Operating Range:
Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
High-Performance DSC CPU:
Modified Harvard architecture
C compiler optimized instruction set
16-bit-wide data path
24-bit-wide instructions
Linear program memory addressing up to 4M
instruction words
Linear data memory addressing up to 64 Kbytes
83 base instructions: mostly one word/one cycle
Two 40-bit accumulators with rounding and
saturation options
Flexible and powerful addressing modes:
-Indirect
- Modulo
- Bit-Reversed
Software stack
16 x 16 fractional/integer multiply operations
32/16 and 16/16 divide operations
Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Up to ±16-bit shifts for up to 40-bit data
Timers/Capture/Compare/PWM:
Timer/Counters, up to three 16-bit timers
- Can pair up to make one 32-bit timer
- One timer runs as Real-Time Clock with
external 32.768 kHz oscillator
- Programmable prescaler
Input Capture (up to four channels):
- Capture on up, down, or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
Output Compare (up to two channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
Interrupt Controller:
5-cycle latency
Up to 26 available interrupt sources
Up to three external interrupts
Seven programmable priority levels
Four processor exceptions
Digital I/O:
Peripheral pin Select functionality
Up to 21 programmable digital I/O pins
Wake-up/Interrupt-on-Change for up to 21 pins
Output pins can drive from 3.0V to 3.6V
Up to 5V output with open drain configurations on
5V tolerant pins
4 mA sink on all I/O pins
On-Chip Flash and SRAM:
Flash program memory (12 Kbytes)
Data SRAM (1024 bytes)
Boot and General Security for program Flash
System Management:
Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low-jitter PLL
Power-up Timer
Oscillator Start-up Timer/Stabilizer
Watchdog Timer with its own RC oscillator
Fail-Safe Clock Monitor
Reset by multiple sources
Power Management:
On-chip 2.5V voltage regulator
Switch between clock sources in real time
Idle, Sleep, and Doze modes with fast wake-up
High-Performance, 16-bit Digital Signal Controllers
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