參數(shù)資料
型號: DSPIC33FJ12MC202-I/SO
廠商: Microchip Technology
文件頁數(shù): 90/155頁
文件大小: 0K
描述: IC DSPIC MCU/DSP 12K 28SOIC
產品培訓模塊: Asynchronous Stimulus
特色產品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標準包裝: 27
系列: dsPIC™ 33F
核心處理器: dsPIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: I²C,IrDA,SPI,UART/USART
外圍設備: 高級欠壓探測/復位,電機控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 12KB(12K x 8)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據轉換器: A/D 6x10b/12b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產品目錄頁面: 651 (CN2011-ZH PDF)
配用: AC164339-ND - MODULE SKT FOR PM3 28SOIC
DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32
dsPIC33FJ12MC201/202
DS70265E-page 4
2007-2011 Microchip Technology Inc.
Motor Control Peripherals:
6-channel 16-bit Motor Control PWM:
- Three duty cycle generators
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
2-channel 16-bit Motor Control PWM:
- One duty cycle generator
- Independent or Complementary mode
- Programmable dead time and output polarity
- Edge-aligned or center-aligned
- Manual output override control
- One Fault input
- Trigger for ADC conversions
- PWM frequency for 16-bit resolution
(@ 40 MIPS) = 1220 Hz for Edge-Aligned
mode, 610 Hz for Center-Aligned mode
- PWM frequency for 11-bit resolution
(@ 40 MIPS) = 39.1 kHz for Edge-Aligned
mode, 19.55 kHz for Center-Aligned mode
Quadrature Encoder Interface module:
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
Analog-to-Digital Converters (ADCs):
10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to six input channels with auto-scanning
- Conversion start can be manual or
synchronized with one of four trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology:
Low-power, high-speed Flash technology
Fully static design
3.3V (±10%) operating voltage
Industrial and Extended temperature
Low power consumption
Communication Modules:
4-wire SPI:
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
I2C:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
UART:
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
-IrDA encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Packaging:
20-pin PDIP/SOIC/SSOP
28-pin SPDIP/SOIC/SSOP/QFN
Note:
See Table 1 for the exact peripheral
features per device.
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