- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄21331 > DSPIC33FJ16GP304T-I/PT (Microchip Technology)IC DSPIC MCU/DSP 16K 44TQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | DSPIC33FJ16GP304T-I/PT |
| 廠(chǎng)商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 33/176頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSPIC MCU/DSP 16K 44TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 1,200 |
| 系列： | dsPIC™ 33F |
| 核心處理器： | dsPIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 35 |
| 程序存儲(chǔ)器容量： | 16KB（16K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 13x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 帶卷 (TR) |
| 配用： | DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 DM240001-ND - BOARD DEMO PIC24/DSPIC33/PIC32 |
| 其它名稱(chēng)： | DSPIC33FJ16GP304T-I/PTTR |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)當(dāng)前第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)
126
AT89C5131
4136C–USB–04/05
Isochronous Transactions
Isochronous OUT
Transactions in Standard
Mode
An endpoint will be first enabled and configured before being able to receive Isochro-
nous packets.
When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB
controller. This triggers an interrupt if enabled. The firmware has to select the corre-
sponding endpoint, store the number of data bytes by reading the UBYCTLX and
UBYCTHX registers. If the received packet is a ZLP (Zero Length Packet), the
UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUTB0
bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO.
Until the RXOUTB0 bit has been cleared by the firmware, the data sent by the Host at
each OUT transaction will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data, the USB controller will
store only the remaining bytes into the FIFO.
If the Host sends more bytes than supported by the endpoint FIFO, the overflow data
won’t be stored, but the USB controller will consider that the packet is valid if the CRC is
correct.
Isochronous OUT
Transactions in Ping-pong
Mode
An endpoint will be first enabled and configured before being able to receive Isochro-
nous packets.
When a OUT packet is received on the endpoint bank 0, the RXOUTB0 bit is set by the
USB controller. This triggers an interrupt if enabled. The firmware has to select the cor-
responding endpoint, store the number of data bytes by reading the UBYCTLX and
UBYCTHX registers. If the received packet is a ZLP (Zero Length Packet), the
UBYCTLX and UBYCTHX register values are equal to 0 and no data has to be read.
The STLCRC bit in the UEPSTAX register is set by the USB controller if the packet
stored in FIFO has a corrupted CRC. This bit is updated after each new packet receipt.
When all the endpoint FIFO bytes have been read, the firmware will clear the RXOUB0
bit to allow the USB controller to store the next OUT packet data into the endpoint FIFO
bank 0. This action switches the endpoint bank 0 and 1. Until the RXOUTB0 bit has
been cleared by the firmware, the data sent by the Host on the bank 0 endpoint FIFO
will be lost.
If the RXOUTB0 bit is cleared while the Host is sending data on the endpoint bank 0, the
USB controller will store only the remaining bytes into the FIFO.
When a new OUT packet is received on the endpoint bank 1, the RXOUTB1 bit is set by
the USB controller. This triggers an interrupt if enabled. The firmware empties the bank
1 endpoint FIFO before clearing the RXOUTB1 bit. Until the RXOUTB1 bit has been
cleared by the firmware, the data sent by the Host on the bank 1 endpoint FIFO will be
lost.
The RXOUTB0 and RXOUTB1 bits are alternatively set by the USB controller at each
new packet receipt.
The firmware has to clear one of these two bits after having read all the data FIFO to
allow a new packet to be stored in the corresponding bank.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| P51-300-A-Y-D-4.5V-000-000 | SENSOR 300PSI 7/16-20-2B .5-4.5V |
| P51-15-G-UCA-MD-5V-000-000 | SENSOR 15PSI 7/16-20UNF 1-5V |
| P51-50-S-H-P-20MA-000-000 | SENSOR 50PSIS M12 4-20 MA |
| P51-1000-A-S-D-4.5OVP-000-000 | SENSOR 1000PSI 1/4-18NPT .5-4.5V |
| DSPIC33FJ32GP202T-I/SO | IC DSPIC MCU/DSP 32K 28SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| dsPIC33FJ16GS402-50I/MM | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU/DSP 50MIPS 16KB FL SMPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ16GS402-50I/SO | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU/DSP 50MIPS 16KB FL SMPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ16GS402-50I/SP | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU/DSP 50MIPS 16KB FL SMPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ16GS402-E/MM | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU/DSP 28 LD 40MIPS 16 KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| dsPIC33FJ16GS402-E/SO | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B MCU/DSP 28 LD 40MIPS 16 KB FLASH RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。