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參數(shù)資料
| 型號(hào)： | DT28F160S3-120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 16 Characters x 2 Lines, 5x7 Dot Matrix Character and Cursor |
| 中文描述： | 1M X 16 FLASH 2.7V PROM, 120 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數(shù)： | 31/52頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | DT28F160S3-120 |
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E
28F160S3, 28F320S3
31
ADVANCE INFORMATION
Table 15. Status Register Definition
WSMS
ESS
ECLBS
BWSLBS
VPPS
BWSS
DPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS in RY/BY# mode or SR.7 to determine
block erase, programming, or lock-bit configuration
completion. SR.6-0 are invalid while SR.7 =
“0.”
SR.6 = ERASE SUSPEND STATUS
1 = Block erase suspended
0 = Block erase in progress/completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS
1 = Error in block erasure or clear lock-bits
0 = Successful block erase or clear lock-bits
If both SR.5 and SR.4 are
“1”s after a block erase
or lock-bit configuration attempt, an improper
command sequence was entered.
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in program or block lock-bit
0 = Successful program or set block lock-bit
SR.3 = V
PP
STATUS
1 = V
PP
low detect, operation abort
0 = V
PP
OK
SR.3 does not provide a continuous indication of
V
PP
level. The WSM interrogates and indicates the
V
PP
level only after a block erase, program, or lock-
bit configuration operation. SR.3 reports accurate
feedback only when V
PP
= V
PPH1/2
.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program suspended
0 = Program in progress/completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or
RP# lock detected, operation abort
0 = Unlock
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bit, and WP# only after a block erase,
program, or lock-bit configuration operation. It
informs the system, depending on the attempted
operation, if the block lock-bit is set.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.0 is reserved for future use and should be
masked when polling the Status Register.
Table 16. Extended Status Register Definition
WBS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
NOTES:
XSR.7 = WRITE BUFFER STATUS
1 = Write to buffer available
0 = Write to buffer not available
After a Write to buffer command, XSR.7 indicates
that another Write to buffer command is possible.
XSR.6 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.6–0 are reserved for future use and should be
masked when polling the status register
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相關(guān)代理商/技術(shù)參數(shù) |
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| DT28F160S3-130 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| DT28F160S3-75 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
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| DT28F320J5120 | 制造商:INTEL 功能描述:_ |
| DT28F320J5-120 | 制造商:INTEL 功能描述:_ |
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