參數(shù)資料
型號(hào)： DT28F800F3T120
廠商： INTEL CORP
元件分類： DRAM
英文描述： FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
中文描述： 512K X 16 FLASH 2.7V PROM, 120 ns, PDSO56
封裝： 16 X 23.70 MM, SSOP-56
文件頁數(shù)： 20/47頁
文件大?。?/td> 277K
代理商： DT28F800F3T120
FAST BOOT BLOCK DATASHEET
E
20
PRODUCT PREVIEW
synchronous burst-mode. Bit RCR.15 in the read
configuration register sets the read configuration.
Asynchronous page-mode is the default read
configuration state.
Parameter blocks, status register, and identifier
only support single asynchronous and synchronous
read operations.
4.9.2
FREQUENCY CONFIGURATION
The frequency configuration informs the device of
the number of clocks that must elapse after ADV#
is driven active before data will be available. This
value is determined by the input clock frequency.
See Table 7 for the specific input CLK frequency
configuration code
Figure 5 illustrates data output latency from ADV#
going active for different frequency configuration
codes.
4.9.3
DATA OUTPUT CONFIGURATION
The output configuration determines how many
clocks data will be held valid. The data hold time is
configurable as either one or two clocks.
The data output configuration must be set to hold
data valid for two clock cycles when the frequency
configuration value 4 and burst length is greater
than four words. Otherwise, its setting will depend
on the system CPU’s data setup requirement.
DQ
15-0
(D/Q)
Valid
Output
DQ
15-0
(D/Q)
Valid
Output
Valid
Output
Valid
Output
CLK (C)
1 CLK
Data Hold
2 CLK
Data hold
Figure 6. Output Configuration
4.9.4
WAIT# CONFIGURATION
The WAIT# configuration bit controls the behavior
of the WAIT# output signal. This output signal can
be set to be asserted during or one CLK cycle
before an output delay when continuous burst
length is enabled. Its setting will depend on the
system and CPU characteristic.
4.9.5
BURST SEQUENCE
The burst sequence specifies the order in which
data is addressed in synchronous burst-mode. This
order is programmable as either linear or Intel burst
order. The continuous burst length only supports
linear burst order. The order chosen will depend on
the CPU characteristic. See Table 8 for more
details.
4.9.6
CLOCK CONFIGURATION
The clock configuration configures the device to
start a burst cycle, output data, and assert WAIT#
on the rising or falling edge of the clock. CLK
flexibility helps ease Fast Boot Block flash memory
interface to wide range of burst CPUs.
4.9.7
BURST LENGTH
The burst length is the number of words that the
device will output. The device supports burst
lengths of four and eight words. It also supports a
continuous burst mode. In continuous burst mode,
the device will linearly output data until the internal
burst counter reaches the end of the device’s
burstable address space. Bits RCR.2–0 in the read
configuration register set the burst length.
4.9.7.1
Continuous Burst Length
When operating in the continuous burst mode, the
flash memory may incur an output delay when the
burst sequence crosses the first sixteen word
boundary. The starting address dictates whether or
not a delay will occur. If the starting address is
aligned to a four word boundary, the delay will not
be seen. If the starting address is the end of a four
word boundary, the output delay will be equal to the
frequency configuration setting; this is the worst
case delay. The delay will only take place once
during a continuous burst access, and if the burst
sequence never crosses a sixteen word boundary,
the delay will never happen. Using the WAIT#
output pin in the continuous burst configuration, the
system is informed if this output delay occurs.
相關(guān)PDF資料
PDF描述
DT28F800F3T95 FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT
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