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參數(shù)資料
| 型號(hào)： | DT28F800F3T120 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 512K X 16 FLASH 2.7V PROM, 120 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁(yè)數(shù)： | 22/47頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | DT28F800F3T120 |
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FAST BOOT BLOCK DATASHEET
E
22
PRODUCT PREVIEW
Suspend
Blk. Erase
Loop
Start
Write 20H,
Block Address
Write D0H,
Block Address
Read Status Register
SR.7 =
Full Status
Check if Desired
Block Erase Complete
FULL STATUS CHECK PROCEDURE
Repeat for subsequent block erasures.
Full status check can be done after each block erase or after a
sequence of block erasures.
Write FFH after the last operation to place device in read array mode.
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Staus
Register command, in cases where multiple blocks are erased before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
No
Yes
Suspend
Block Erase
1
0
Comments
Data = 20H
Addr = Within Block to Be
Erased
Data = D0H
Addr = Within Block to Be
Erased
Check SR.7
1 = WSM Ready
0 = WSM Busy
Comments
Check SR.3
1 = V
PP
Error Detect
Check SR.1
1 = Device Protect Detect
WP# = V
IL
Read Status Register
Data (See Above)
V
PP
Range Error
Device Protect Error
Block Erase
Successful
SR.3 =
SR.1 =
1
0
1
0
Command Sequence
Error
SR.4, 5 =
1
0
Block Erase Error
SR.5 =
1
0
Status Register Data
Check SR.4, 5
Both 1 = Command Sequence
Error
Check SR.5
1 = Block Erase Error
Bus Operation
Write
Write
Standby
Read
Command
Erase Setup
Erase Confirm
Bus Operation
Standby
Standby
Standby
Standby
Command
Figure 7. Automated Block Erase Flowchart
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PDF描述 |
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| DT28F800F3T95 | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
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