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參數資料
| 型號： | DT28F800F3T95 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | FAST BOOT BLOCK FLASH MEMORY FAMILY 8 AND 16 MBIT |
| 中文描述： | 512K X 16 FLASH 2.7V PROM, 95 ns, PDSO56 |
| 封裝： | 16 X 23.70 MM, SSOP-56 |
| 文件頁數： | 14/47頁 |
| 文件大?。?/td> | 277K |
| 代理商： | DT28F800F3T95 |
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FAST BOOT BLOCK DATASHEET
E
14
PRODUCT PREVIEW
Table 3. Command Definitions
(1)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req’d.
Notes
Oper
(2)
Addr
(3)
Data
(4)
Oper
(2)
Addr
(3)
Data
(4)
Read Array/Reset
1
Write
X
FFH
Read Identifier Codes
≥
2
2
5
Write
X
90H
Read
IA
ID
Read Status Register
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
6,7
Write
X
20H
Write
BA
D0H
Program
2
6,7,8
Write
X
40H
or
10H
Write
WA
WD
Block Erase and Program
Suspend
1
6
Write
X
B0H
Block Erase and Program
Resume
1
6
Write
X
D0H
Set Read Configuration
2
Write
X
60H
Write
RCD
03H
NOTES:
1.
2.
3.
Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
Bus operations are defined in Table 2.
X = Any valid address within the device.
IA = Identifier Code Address.
BA = Address within the block being erased.
WA = Address of memory location to be written.
RCD = Data to be written to the read configuration register. This data is presented to the device on A
15-0
; set all other
address inputs to
“0.”
SRD = Data read from status register. See Table 5 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes. See Table 4 for manufacturer and device codes.
RCD = Data to be written to read configuration register. See Table 6 for a description of the read configuration register bits.
Following the Read Identifier Codes command, read operations access manufacturer, device codes, and read
configuration register.
Following a block erase, program, and suspend operation, read operations access the status register.
To issue a block erase, program, or suspend operation to a lockable block, hold WP# at V
IH
.
Either 40H or 10H are recognized by the WSM as the program setup.
4.
5.
6.
7.
8.
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