905
SAM4CP [DATASHEET]
43051E–ATPL–08/14
40.
Analog-to-Digital Converter (ADC)
40.1
Description
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to
Figure 40-1,
"Analog-to-Digital Converter Block Diagram"
. It also integrates an 8-to-1 analog multiplexer, making possible the
analog-to-digital conversions of 8
analog lines. The conversions extend from 0V to the voltage carried on pin ADVREF or
the voltage provided by the internal reference voltage which can be programmed in the Analog Control register
(ADC_ACR). The selection of reference voltage source is defined by ONREF and FORCEREF bits in the Mode Register
(ADC_MR).
The ADC supports the 8-bit or 10-bit resolution mode. The 8-bit resolution mode prevents using the 16-bit peripheral
DMA transfer into memory when only 8-bit resolution is required by the application. Note that using this low resolution
mode does not increase the conversion rate.
Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
The 11-bit and 12-bit resolution modes are obtained by averaging multiple samples to decrease quantization noise. For
11-bit mode, four samples are used, which gives an effective sample rate of 1/4 of the actual sample frequency. For
12-bit mode, 16 samples are used, giving an effective sample rate of 1/16th of the actual sample frequency.This allows
conversion speed to be traded for better accuracy.
The last channel is internally connected to a temperature sensor. The processing of this channel can be fully configured
for efficient downstream processing due to the slow frequency variation of the value carried on such a sensor. The
seventh channel is reserved for measurement of VDDBU voltage.
The software trigger, the external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter
output(s) are configurable.
The main comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given
range or outside the range. Thresholds and ranges are fully configurable.
The ADC also integrates a sleep mode and a conversion sequencer, and connects with a PDC channel. These features
reduce both power consumption and processor intervention.
Finally, the user can configure ADC timings, such as startup time and tracking time.
Note: Please check ADC available signals in the main Block Diagram
Figure 2-1
.
40.2
Embedded Characteristics
10-bit Resolution with Enhanced Mode up to 12 Bits.
500 kHz Conversion Rate.
Digital Averaging Function Provides Enhanced Resolution Mode up to 12 Bits.
On-chip Temperature Sensor Management.
Wide Range of Power Supply Operation.
Selectable External Voltage Reference or Programmable Internal Reference.
Integrated Multiplexer Offering Up to 8 Independent Analog Inputs.
Individual Enable and Disable of Each Channel.
Hardware or Software Trigger.
External Trigger Pin.
Timer Counter
Outputs (Corresponding TIOA
Trigger).
PDC Support.
Possibility of ADC Timings Configuration.
Two Sleep Modes and Conversion Sequencer.
Automatic Wake-up on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels.
Possibility of Customized Channel Sequence.
Standby Mode for Fast Wakeup Time Response.
Power Down Capability.
Automatic Window Comparison of Converted Values.
Register Write Protection.