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P7/14
ECN30102 Product Specification
ECN30102
3.3 PWM Opertion
The PWM signal is generated by comparing input voltage at the VSP terminal with an internal
triangular wave voltage (available at CR pin). The Duty cycle of the resulting PWM signal is thus
directly controlled by VSP terminal voltage: from the VSAWL to the VSAWH. That is, when VSP
is below VSAWL, PWM duty cycle sits at 0%; when VSP is above VSAWH, PWM duty sits at
100%. The ECN30204 operats in 2 quadrants by chopping (only) the Bottom Arms with this
generated PWM duty cycle during their appropriate commutation time (phase). PWM duty cycle
thus controls motor torque and speed.
3.4 Over current limiting operation
This IC detects over current by checking the voltage drop across an external resistance Rs. When
RS input voltage exceeds internal reference voltage Vref, all bottom arms are turned-off output.
After over current event, reset is automatically attempted at each period of the internal clock signal
period. The internal clock signal is available at the VTR terminal.
In case of not using this function,
please connect Rs terminal to GL terminal less than 100
impedance.
3.5 VCC under voltage Detection
When the VCC supply voltage drops below LVSDON, all IGBTs turned-off. Normal operation returns
when the VCC voltage rises above LVSDOFF, the value of LVSDOFF is (LVSDON + Vrh).
3.6 All output IGBTs shut-off function
When VSP terminal voltage drops below Voff, all IGBTs shut-off.
VSP input voltage
Top arm outputs
Bottom arm outputs
0V
≤ VSP < Voff
All IGBTs are off
Voff
≤ VSP < VSAWL Following item 3.1) Truth Table
All IGBTs are off
VSP
≥ VSAWL Following item 3.1) Truth Table
Following item 3.1) Truth Table
If VSP terminal voltage drops below Voff while the motor is rotating, the motor will stop. Under
this condition, the VS voltage could rise but, in all cases, VS must not exceed the ECN30102,
250VDC breakdown voltage.
PDE-30102-2
Relation No.:IC-SP-01017 R2