USB Description 1 USB clock divider logic operates at a maximum rate of 288 MHz under worst case conditions. Workaround When using " />
參數(shù)資料
型號: EDB9301
廠商: Cirrus Logic Inc
文件頁數(shù): 4/5頁
文件大?。?/td> 0K
描述: KIT DEVELOPMENT EP9301 ARM9
標準包裝: 1
其它名稱: 598-1131
4
ER636E2
B
USB
Description 1
USB clock divider logic operates at a maximum rate of 288 MHz under worst case conditions.
Workaround
When using USB, make sure the clock frequency supplied to the USB clock divider does not exceed 288
MHz. The clock supplied to the USB clock divider is sourced by PLL2. The USB clock divider is controlled
by the USBDIV setting in the CLKSET2 register. For example, configure PLL2 to output 192MHz and
USBDIV to divide by four. Ensure that the new PLL2 setting does not adversely affect any other block using
PLL2 as its clock source.
NOTE: PLL2 is completely functional. This is only an issue with the USB clock divider logic.
ExtensionID Register
Description
The PartID field in register 0x8083_2714, ExtensionID, is not programmed.
Workaround
None, this register has been de-featured from the chip.
Reset
Description
The processor may boot into an invalid state upon initial power up of the device. When this condition occurs,
the processor will not complete its boot sequence and requires an additional power on reset (POR) to be
applied.
Workaround
Implement the recommended external reset circuit described in AN258, “EP93xx Power-up and Reset
Lockup Workaround,” which can be found at http://www.cirrus.com/en/pubs/appNote/AN258REV2.pdf.
Boot Configuration
Description
The processor may incorrectly latch the state of the CSn[7:6, 3:0] lines. The only problematic effect of this
condition is that the device may attempt to perform a 32-bit boot when it is actually configured for 16-bit boot
mode.
Workaround
Implement the recommendations described in AN273, item 7, “EP93xx Silicon Rev E Design Guidelines,”
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