參數(shù)資料
型號(hào): EDD5116AFTA-6B-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 512M bits DDR SDRAM
中文描述: 32M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-66
文件頁(yè)數(shù): 26/49頁(yè)
文件大?。?/td> 567K
代理商: EDD5116AFTA-6B-E
EDD5108AFTA, EDD5116AFTA
Data Sheet E0699E20 (Ver. 2.0)
26
Auto Precharge
Read with auto-precharge
The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2)
cycle after READA command input.
tRAP specification for READA allows a read command with auto precharge to be
issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column
command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge
command does not limit row commands execution for other bank. Refer to ‘Function truth table and related notes
(Notes.*14)‘.
out0
out1
out2
out3
CK
/CK
DQ
Command
tRP (min)
tRAP (min) = tRCD (min)
ACT
Note: Internal auto-precharge starts at the timing indicated by " ".
NOP
2 cycles (= BL/2)
READA
ACT
DQS
tAC,tDQSCK
tRPD
Read with auto-precharge
Write with auto-precharge
The precharge is automatically performed after completing a burst write operation. The precharge operation is
started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the
next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row
commands execution for other bank. Refer to ‘Function truth table and related notes (Notes.*14)‘.
in1
in2
in3
in4
CK
/CK
DQ
Command
DM
tRAS (min)
tRCD (min)
tRP
DQS
ACT
WRITA
ACT
BL/2 + 3 cycles
Note: Internal auto-precharge starts at the timing indicated by " ".
BL = 4
NOP
NOP
Burst Write (BL = 4)
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