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參數(shù)資料
| 型號(hào)： | EDI2CG472128V-D2 |
| 英文描述： | SSRAM Modules |
| 中文描述： | 的SSRAM模塊 |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 172K |
| 代理商： | EDI2CG472128V-D2 |
EDI2CG272128V
4
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
August 2000 Rev.0
ECO#13088
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1
E2
ADSP
ADSC
ADV
GW
G
CLK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
L
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
H
L
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
L
X
L-H
D
Current
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDI2CG472256V-D2 | SSRAM Modules |
| EDI2CG272128V12D1 | 2x128Kx72, 3.3V S nc/S nc Burst Flow-Through(2x128Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG272128V15D1 | 2x128Kx72, 3.3V S nc/S nc Burst Flow-Through(2x128Kx72, 3.3V，15ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG272128V85D1 | 2x128Kx72, 3.3V Sync/Sync Burst Flow-Through(2x128Kx72, 3.3V，8.5ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
| EDI2CG272128V9D1 | 2x128Kx72, 3.3V S nc/S nc Burst Flow-Through(2x128Kx72, 3.3V，9ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDI2CG472256V | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V10D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V12D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V15D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
| EDI2CG472256V9D2 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8 Megabyte Sync/Sync Burst, Dual Key DIMM |
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