參數(shù)資料
型號： EDI2CG472256V12D2
英文描述： 4x256Kx72, 3.3V Synchronous/Synchronous Burst Flow-Through(4x256Kx72, 3.3V，12ns,同步/同步脈沖靜態(tài)RAM模塊(流通結(jié)構(gòu)）)
中文描述： 4x256Kx72，3.3同步/同步突發(fā)流量通過（4x256Kx72，3.3伏，12ns，同步/同步脈沖靜態(tài)內(nèi)存模塊（流通結(jié)構(gòu)））
文件頁數(shù)： 8/12頁
文件大小： 366K
代理商： EDI2CG472256V12D2
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
EDI2CG472256V
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1\
E2\
E3\
E4\
ADSP\ ADSC\
ADV\
GW\
G\
CLK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
*
X
L
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
*
X
L
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
*
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
L
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
L
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
*
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
*
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
*
H
L
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
*
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
*
H
L
X
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
*
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
*
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
*
X
H
L
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
*
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
*
X
H
L
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
*
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
*
X
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
*
H
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
*
X
H
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
*
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
*
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
*
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
*
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
*
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
*
X
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
*
X
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
*
X
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
*
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
*
X
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
*
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
*
X
H
L
X
L-H
D
Current
*All Truth Table Functions Repeat for Bank 3 (E3\) and Bank 4 (E4\)
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