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參數(shù)資料
| 型號： | EDI2GG41864V15D |
| 英文描述： | 4x64Kx18 3.3V Synchronous SRAM Card Module(4x64Kx18, 3.3V，15ns,同步靜態(tài)RAM卡模塊(流通結(jié)構(gòu)）) |
| 中文描述： | 4x64Kx18 3.3同步SRAM卡模塊（4x64Kx18，3.3伏，15納秒，同步靜態(tài)內(nèi)存卡模塊（流通結(jié)構(gòu)）） |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 1529K |
| 代理商： | EDI2GG41864V15D |
4
White Electronic Designs Corporation Westborough, MA 01581
(508) 366-5151 www.whiteedc.com
EDI2GG41864V
July 1999 Rev ECO
PIN DESCRIPTIONS
DIMM Pins
3, 5, 7, 9, 13, 15,
17, 19, 23, 20, 18,
16, 14, 10, 8, 6
38
Symbol
A0-A17
Type
Input
Description
Addresses: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. The burst counter generates internal
addresses associated with A0 and A1, during burst and wait cycle.
Global Write: This active LOW input allows a full 72-bit WRITE to occur
independent of the BWE\ and BWx\ lines and must meet the setup and hold
times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables, write control
and burst control inputs on its rising edge. All synchronous inputs must
meet setup and hold times around the clock’s rising edge.
Bank Enables: These active LOW inputs are used to enable each
individual bank and to gate ADSP\.
Output Enable: This active LOW asynchronous input enables the data output
drivers.
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is
DQ16-23, fourth byte is DQ24-31, fifth byte is DQ32-39, sixth byte is
DQ40-47, seventh byte is DQ48-55 and the eight byte is DQ56-64.
Core power supply: +3.3V -5%/+10%
Ground
Synchronous
GW\
Input
Synchronous
27
CLK
Input
Synchronous
36, 32,
35, 31
37
E1\, E2\
E3\, E4\
G\
Input
Synchronous
Input
Various
DQ0-63
Input/Output
Various
Various
Vcc
Vss
Supply
Ground
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