參數(shù)資料
型號: EDS6416AJTA-75-E
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù): 9/49頁
文件大?。?/td> 622K
代理商: EDS6416AJTA-75-E
EOL
Product
EDS6416AJTA
Data Sheet E0884E30 (Ver.3.0)
17
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Mode register set
H
×
DESL
NOP
L
H
×
NOP
L
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
4
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
4
L
H
BA, RA
ACT
Bank and row active*
9
L
H
L
BA, A10
PRE, PALL
NOP
L
H
×
REF, SELF
Refresh*
9
L
MODE
MRS
Mode register set*
8
Remark: H: VIH. L: VIL.
×: VIH or VIL
Notes: 1. An interval of tDPL is required between the final valid data input and the precharge command.
2. If tRRD is not satisfied, this operation is illegal.
3. Illegal for same bank, except for another bank.
4. Illegal for all banks.
5. NOP for same bank, except for another bank.
6. Illegal if tRCD is not satisfied.
7. Illegal if tRAS is not satisfied.
8. MRS command must be issued after DOUT finished, in case of DOUT remaining.
9. Illegal if lMRD is not satisfied.
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