參數(shù)資料
型號： EFM32G232F128
廠商： Energy Micro
文件頁數(shù)： 72/136頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB FLASH 64LQFP
標準包裝： 1
系列： Gecko
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 32MHz
連通性： I²C，IrDA，智能卡，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲器容量： 128KB（128K x 8）
程序存儲器類型： 閃存
RAM 容量： 16K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 1x12b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 標準包裝
其它名稱： 914-1026-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
40
www.energymicro.com
directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination
register
during the calculation of Operand2 by the instructions that specify the second operand as a register
with shift, see Section 3.3.3 (p. 38) . The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction, see the individual instruction
description or Section 3.3.3 (p. 38) . If the shift length is 0, no shift occurs. Register shift operations
update the carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register
containing the value to be shifted, and n is the shift length.
3.3.4.1 ASR
Arithmetic shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places,
into the right-hand 32-n bits of the result. And it copies the original bit[31] of the register into the left#hand
n
bits of the result. See Figure 3.1 (p. 40) .
You can use the ASR #n operation to divide the value in the register Rm by 2
n, with the result being
rounded towards negative-infinity.
When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS
, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Note
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of Rm.
Figure 3.1. ASR #3
31
1 0
Carry
Flag
...
2
3
4
5
3.3.4.2 LSR
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by n places, into
the right-hand 32-n bits of the result. And it sets the left#hand n bits of the result to 0. See Figure 3.2 (p.
You can use the LSR #n operation to divide the value in the register Rm by 2
n, if the value is regarded
as an unsigned integer.
When the instruction is LSRS or when LSR #n is used in Operand2 with the instructions MOVS, MVNS,
ANDS
, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Note
If n is 32 or more, then all the bits in the result are cleared to 0.
If n is 33 or more and the carry flag is updated, it is updated to 0.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EFM32G232F128G-E-QFP64R 功能描述:128K FLASH, 16K RAM, AES 制造商:silicon labs 系列:Gecko 包裝:剪切帶（CT） 零件狀態(tài):在售 核心處理器:ARM? Cortex?-M3 核心尺寸:32-位 速度:32MHz 連接性:I2C，IrDA，智能卡，SPI，UART/USART 外設(shè):欠壓檢測/復(fù)位，DMA，POR，PWM，WDT I/O 數(shù):53 程序存儲容量:128KB（128K x 8） 程序存儲器類型:閃存 EEPROM 容量:- RAM 容量:16K x 8 電壓 - 電源（Vcc/Vdd）:1.98 V ~ 3.8 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x12b，D/A 1x12b 振蕩器類型:內(nèi)部 工作溫度:-40°C ~ 85°C（TA） 封裝/外殼:64-TQFP 供應(yīng)商器件封裝:64-TQFP（10x10） 標準包裝:1
EFM32G232F128-QFP64 制造商:Energy Micro AS 功能描述:GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64TQFP
EFM32G232F128-QFP64T 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, GECKO - Trays
EFM32G232F128-QFP64-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64TQFP
EFM32G232F128-T 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 128KB FLASH 64TQFP
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