參數(shù)資料
型號(hào): EFM32TG222F32
廠商: Energy Micro
文件頁數(shù): 29/136頁
文件大?。?/td> 0K
描述: IC MCU 32BIT 32KB FLASH 48LQFP
特色產(chǎn)品: EFM32 Tiny Gecko
標(biāo)準(zhǔn)包裝: 1
系列: Tiny Gecko
核心處理器: ARM? Cortex?-M3
芯體尺寸: 32-位
速度: 32MHz
連通性: I²C,IrDA,智能卡,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,DMA,I²S,POR,PWM,WDT
輸入/輸出數(shù): 37
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.8 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b,D/A 1x12b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: 914-1029-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
124
www.energymicro.com
Glossary
This glossary describes some of the terms used in technical documents from ARM.
Abort
A mechanism that indicates to a processor that the value associated with a
memory access is invalid. An abort can be caused by the external or internal
memory system as a result of attempting to access invalid instruction or data
memory.
Aligned
A data item stored at an address that is divisible by the number of bytes that
defines the data size is said to be aligned. Aligned words and halfwords have
addresses that are divisible by four and two respectively. The terms word-
aligned and halfword-aligned therefore stipulate addresses that are divisible
by four and two respectively.
Banked register
A register that has multiple physical copies, where the state of the processor
determines which copy is used. The Stack Pointer, SP (R13) is a banked
register.
Base register
In instruction descriptions, a register specified by a load or store instruction
that is used to hold the base value for the instruction’s address calculation.
Depending on the instruction and its addressing mode, an offset can be
added to or subtracted from the base register value to form the address that
is sent to memory.
See Also Index register.
Big-endian (BE)
Byte ordering scheme in which bytes of decreasing significance in a data
word are stored at increasing addresses in memory.
See Also Byte-invariant, Endianness, Little-endian.
Big-endian memory
Memory in which:
a byte or halfword at a word-aligned address is the most significant byte
or halfword within the word at that address
a byte at a halfword-aligned address is the most significant byte within the
halfword at that address.
See Also Little-endian memory.
Breakpoint
A breakpoint is a mechanism provided by debuggers to identify an instruction
at which program execution is to be halted. Breakpoints are inserted by the
programmer to enable inspection of register contents, memory locations,
variable values at fixed points in the program execution to test that the
program is operating correctly. Breakpoints are removed after the program
is successfully tested.
Byte-invariant
In a byte-invariant system, the address of each byte of memory remains
unchanged when switching between little-endian and big-endian operation.
When a data item larger than a byte is loaded from or stored to memory,
the bytes making up that data item are arranged into the correct order
depending on the endianness of the memory access. An ARM byte-
invariant implementation also supports unaligned halfword and word memory
accesses. It expects multi-word accesses to be word-aligned.
Cache
A block of on-chip or off-chip fast access memory locations, situated between
the processor and main memory, used for storing and retrieving copies of
often used instructions, data, or instructions and data. This is done to greatly
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