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參數(shù)資料
型號(hào): EL1508CL
廠商: Intersil
文件頁數(shù): 6/18頁
文件大?。?/td> 0K
描述: IC LINE DRIVER ADSL 24-QFN
標(biāo)準(zhǔn)包裝: 90
類型: 驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 1/0
電源電壓: 5 V ~ 12 V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(5x4)
包裝: 帶卷 (TR)
14
FN7014.5
March 26, 2007
combination of the quiescent power and the output stage
power when driving the line:
In the full power mode and with 6.8k RADJ registers, the
EL1508 consumes typically 7mA quiescent current and still
able to maintain very low distortion. The distortion results are
shown in typical performance section of the data sheet.
When driving a load, a large portion (about 50%) of the
quiescent current becomes output load current:
where:
Pd = 598mW
The
θ
JA requirement needs to be calculated. This is done
using the equation:
where:
TJUNCT is the maximum die temperature (150°C)
TAMB is the maximum ambient temperature (85°C)
PDISS is the dissipation calculated above
θ
JA is the junction to ambient thermal resistance for the
package when mounted on the PCB
PCB Layout Considerations for QFN and SOIC
Packages
The EL1508 die is packaged in three different thermally-
efficient packages: a 20 Ld SOIC (0.300”), a 16 Ld SOIC
(0.150”), and a 24 Ld QFN. The 16 Ld SOIC has the same
external dimensions as a standard 0.150” width SOIC
package, but has the center four leads (two per side)
internally-fused for heat transfer purposes. Both packages
can use PCB surface metal vias areas and internal ground
planes, to spread heat away from the package. The larger
the PCB area the lower the junction temperature of the
device will be. In XDSL applications, multiple layer circuit
boards with internal ground plane are generally used. 13 mil
vias are recommended to connect the metal area under the
device with the internal ground plane. Examples of the PCB
layouts are shown in the figures below that result in thermal
resistance
θJA of 37°C/W for the QFN package and 47°C/W
for the SOIC package. The thermal resistance is obtained
with the EL1508CL and CS demo boards. The demo board
is a 4-layer board built with 2oz. copper and has a dimension
of 4in2. Note, the user must follow the thermal layout
guideline to achieve these results. In addition to lower
thermal resistance, the QFN package exhibits much lower
2nd harmonic distortion.
A separate Application Note for the QFN package and layout
recommendations is also available.
Pd
P
quiescent
P
output-stage
+
=
PdV
S
I
Q
V
S
(
2V
OUT-RMS )
I
OUT-RMS
×
+
×
=
Pd
12
7mA
(
50%
)
12V
(
3.16
) 31.6mA 2
×
+
×
=
Θ
JA
T
JUNCT
T
AMB
P
DISS
--------------------------------------------
=
Θ
JA
150
85
598mW
----------------------
108
°C/W
==
FIGURE 44. TYPICAL ADSL CO LINE DRIVER
IMPLEMENTATION
-
+
-
+
TXFR 1:1
10
RF
1.5k
Ω
100
RT
VS-
VS+
VS-
VS+
3k
2RG
TX+
TX-
FROM
AFE
0.22F
TOP (24 LD QFN)
INTERNAL GROUND PLANE (24 LD QFN)
EL1508
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