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參數(shù)資料
| 型號： | EL1881CSZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO SYNC SEPARATOR 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 97 |
| 類型： | 同步分離器 |
| 應(yīng)用： | 驅(qū)動器，通信，PCMCIA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1247 (CN2011-ZH PDF) |
10
FN7018.2
September 15, 2011
that has a duty cycle of about 15%. Vertical Sync is clocked
out of the EL1881 on the first rising edge during the vertical
serration phase. In the absence of vertical serration pulses,
a vertical sync pulse will be forced out after the vertical sync
default delay time, approximately 60s after the last falling
edge of the vertical equalizing phase for RSET = 681kΩ.
Odd/Even
Because a typical television picture is composed of two
interlaced fields, there is an odd field that includes all the
odd lines, and an even field that consists of the even lines.
This odd/even field information is decoded by the EL1881
during the end of picture information and the beginning of
vertical information. The odd/even circuit includes a
T-flip-flop that is reset during full horizontal lines, but not
during half lines or vertical equalization pulses. The
T-flip-flop is clocked during each falling edge of these
half-period pulses. Even fields will toggle until a low state is
clocked to the odd/even pin 7 at the beginning of vertical
sync, and odd fields will cause a high state to be clocked to
the odd/even pin at the start of the next vertical sync pulse.
Odd/even can be ignored if using non-interlaced video, as
there is no change in timing from one field to the next.
RSET
An external RSET resistor, connected from RSET pin 6 to
ground, produces a reference current that is used internally
as the timing reference for vertical sync width, vertical sync
default delay, burst gate delay and burst width. Decreasing
the value of RSET increases the reference current, which in
turn decreases reference times and pulse widths. A higher
frequency video input necessitates a lower RSET value.
Chroma Filter
A chroma filter is suggested to increase the S/N ratio of the
incoming video signal. Use of the optional chroma filter is
shown in Figure 23. It can be implemented very simply and
inexpensively with a series resistor of 620
Ω and a parallel
capacitor of 500pF, which gives a single pole roll-off
frequency of about 500kHz. This sufficiently attenuates the
3.58MHz (NTSC) or 4.43MHz (PAL) color burst signal, yet
passes the approximately 15kHz sync signals without
appreciable attenuation. A chroma filter will increase the
propagation delay from the composite input to the outputs.
FIGURE 23.
EL1881
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EL1881CSZ-T13 | 功能描述:視頻 IC EL1881CSZ SYNC SEPERATOR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| EL1881CSZ-T7 | 功能描述:視頻 IC EL1881CSZ SYNC SEPERATOR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| EL1881CSZ-T7A | 功能描述:視頻 IC EL1881CSZ SYNC SEPERATOR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| EL1882C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Sync Separator w/50% Slice, AGC |
| EL1882CN | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Sync Separator w/50% Slice, AGC |
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