FN7176.3 August 31, 2010 when sourcing, and when sinking. where: i = 1 to Total number of buffers VS
參數(shù)資料
型號: EL5323CLZ-T7
廠商: Intersil
文件頁數(shù): 5/17頁
文件大小: 0K
描述: IC OPAMP 10CHAN R-R 12MHZ 24-QFN
標(biāo)準(zhǔn)包裝: 1,000
放大器類型: 緩沖器
電路數(shù): 10
輸出類型: 滿擺幅
轉(zhuǎn)換速率: 18 V/µs
-3db帶寬: 12MHz
電流 - 輸入偏壓: 2nA
電壓 - 輸入偏移: 500µV
電流 - 電源: 6.2mA
電流 - 輸出 / 通道: 200mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 16.5 V,±2.25 V ~ 8.25 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN-EP
包裝: 帶卷 (TR)
13
FN7176.3
August 31, 2010
when sourcing, and
when sinking.
where:
i = 1 to Total number of buffers
VS = Total supply voltage
ISMAX = Maximum quiescent current per channel
VOUTi = Maximum output voltage of the application
ILOADi = Load current
If we set the Equations 2 and 3 equal to each other, we can
solve for RLOADi to avoid device overheat. The package
power dissipation curves provide a convenient way to see if
the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equation, it is a simple matter to see if PDMAX exceeds the
device's power derating curves.
Unused Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5123, EL5223, EL5323, and EL5423 can drive a wide
range of capacitive loads. As load capacitance increases,
however, the -3dB bandwidth of the device will decrease and
the peaking increase. The buffers drive 10pF loads in
parallel with 10k
Ω with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5
Ω and
50
Ω) can be placed in series with the output. However, this
will obviously reduce the gain slightly. Another method of
reducing peaking is to add a “snubber” circuit at the output.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. Values of 150
Ω and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current or reduce the gain.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
normal single supply operation, where the VS- pin is
connected to ground, a 0.1F ceramic capacitor should be
placed from VS+ pin to ground. A 4.7F tantalum capacitor
should then be connected from VS+ pin to ground. One
4.7F capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
PDMAX
ΣiV
[
S
ISMAX V
(
OUTiVS- )
ILOADi
×
+
×]
=
(EQ. 3)
EL5123, EL5223, EL5323, EL5423
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