參數(shù)資料
型號： EL5325AIREZ-T13
廠商： INTERSIL CORP
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： 12-Channel TFT-LCD Reference Voltage Generator with External Shutdown
中文描述： 12-OUTPUT THREE TERM VOLTAGE REFERENCE, PDSO28
封裝： ROHS COMPLIANT, MO-153, HTSSOP-28
文件頁數(shù)： 5/12頁
文件大?。?/td> 851K
代理商： EL5325AIREZ-T13
2
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Absolute Maximum Ratings (TA = 25°C)
Supply Voltage between VS & GND . . . . . .4.5V (min) to 18V (max)
Supply Voltage between VSD & GND . 3V (min) to VS and 7V (max)
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = 25°C, unless
otherwise specified.
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
IS
Supply Current
No load
10.2
12.5
mA
ISD
Digital Supply Current
0.17
0.35
mA
ANALOG
VOL
Output Swing Low
Sinking 5mA (VREFH = 15V, VREFL = 0)
50
150
mV
VOH
Output Swing High
Sourcing 5mA (VREFH = 15V, VREFL = 0)
14.85
14.95
V
ISC
Short Circuit Current
RL = 10Ω
100
140
mA
PSRR
Power Supply Rejection Ratio
VS+ is moved from 14V to 16V
45
65
dB
tD
Program to Out Delay
4ms
VAC
Accuracy referred to the ideal value
Code = 512
20
mV
ΔVMIS
Channel to Channel Mismatch
Code = 512
2
mV
VDROOP
Droop Voltage
12
mV/ms
RINH
Input Resistance @ VREFH, VREFL
32
k
Ω
REG
Load Regulation
IOUT = 5mA step
0.5
1.5
mV/mA
CAP
Band Gap
By pass with 0.1F
1
1.3
1.6
V
DIGITAL
VIH
Logic 1 Input Voltage
VSD = 5V
4
V
VSD = 3.3V
2
V
FCLK
Clock Frequency
5MHz
VIL
Logic 0 Input Voltage
VSD = 3.3V/5V
1
V
tS
Setup Time
20
ns
tH
Hold Time
20
ns
tLC
Load to Clock Time
20
ns
tCE
Clock to Load Line
20
ns
tDCO
Clock to Out Delay Time
Negative edge of SCLK
10
ns
RSDIN
SDIN Input Resistance
1G
Ω
TPULSE
Minimum Pulse Width for EXT_OSC Signal
5
s
Duty Cycle
Duty Cycle for EXT_OSC Signal
50
%
INL
Integral Nonlinearity Error
1.3
LSB
DNL
Differential Nonlinearity Error
0.5
LSB
F_OSC
Internal Refresh Oscillator Frequency
OSC_Select = 0
21
kHz
VIH_SHDN
SHDN Voltage Input High
2
V
IIH_SHDN
SHDN Current Input High
SHDN = 2V
100
A
EL5325A
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