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12
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
Table 51. Power-Up Sequencing ............................................................................................. 99
Table 52. DRAM Memory Interface, Page Hit and Refresh Cycle ......................................... 102
Table 53. DRAM First Cycle Read Access ............................................................................. 104
Table 54. DRAM Bank/Page Miss Read Cycles .................................................................... 104
Table 55. DRAM First Cycle Write Access ............................................................................. 106
Table 56. DRAM Bank/Page Miss Write Cycles ..................................................................... 106
Table 57. Local Bus Interface ................................................................................................. 108
Table 58. Video RAM/LCD Interface....................................................................................... 110
Table 59. Power Management Control Signals ...................................................................... 110
Table 60. PCMCIA Memory Read Cycle ................................................................................ 112
Table 61. PCMCIA Memory Write Cycle ................................................................................ 114
Table 62. PCMCIA I/O Read Cycle ........................................................................................ 116
Table 63. PCMCIA I/O Write Cycle ........................................................................................ 118
Table 64. BIOS ROM Read/Write 8-Bit Cycle ........................................................................ 120
Table 65. DOS ROM Read/Write 8-Bit Cycle ......................................................................... 122
Table 66. DOS ROM and Fast DOS ROM Read/Write 16-Bit Cycles .................................... 124
Table 67. ISA Memory Read/Write 8-Bit Cycle ...................................................................... 126
Table 68. ISA Memory Read/Write 16-Bit Cycle .................................................................... 128
Table 69. ISA Memory Read/Write 0 Wait State Cycle .......................................................... 130
Table 70. ISA I/O 8-Bit Read/Write Cycle .............................................................................. 132
Table 71. ISA I/O 16-Bit Read/Write Cycle ............................................................................ 134
Table 72. EPP Data Register Write Cycle .............................................................................. 136
Table 73. EPP Data Register Read Cycle .............................................................................. 137