參數(shù)資料
型號: ELANSC410-100AC
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
中文描述: 32-BIT, FLASH, 100 MHz, MICROCONTROLLER, PBGA292
封裝: PLASTIC, BGA-292
文件頁數(shù): 106/132頁
文件大?。?/td> 2400K
代理商: ELANSC410-100AC
106
élanSC400 and élanSC410 Microcontrollers Data Sheet
t29
t30
t31
t32a
t32b
t33a
t33b
t34
t35
t36
t37
t38
t39
t41
t42
t43
t44
t45
t46
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
Hold, SA, SBHE from read command
Setup, TC to read command deassertion
Hold, TC from read command deassertion
Pulse width, I/O write command
Pulse width, I/O read command
Pulse width, memory read command
Pulse width, memory write command
Delay, MEMR to valid data
Hold, SD from MEMR deassertion
Delay, IOR to valid data
Hold, SD from IOR deassertion
Setup, SD to MEMW assertion
Setup, SD to IOW assertion
Setup, DBUFRDL/DBUFRDH to write command Low
Hold, DBUFRDL/DBUFRDH from write command High
Setup, DBUFRDL/DBUFRDH to read command Low
Hold, DBUFRDL/DBUFRDH from read command High
Setup, DBUFOE Low to write command Low
Hold, DBUFOE from write command High
Setup, DBUFOE Low to read command Low
Hold, DBUFOE from read command High
Setup, DBUFRDL/DBUFRDH to mem read command Low, DMA
Hold, DBUFRDL/DBUFRDH from mem read command High, DMA
Setup, DBUFOE Low to mem read command Low, DMA
Hold, DBUFOE from mem read command High, DMA
Setup, DBUFRDL/DBUFRDH to I/O read command Low, DMA
Setup, DBUFOE Low to I/O read command Low, DMA
Hold, DBUFOE from I/O read command High, DMA
Hold, DBUFRDL/DBUFRDH from I/O read command High, DMA
53
470
60
400
700
800
470
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
272
11
241
11
-21
-214
45
30
0
10
45
30
0
10
0
10
0
10
0
0
10
10
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
1. These parameters are applicable only when an external data transceiver is used to isolate the SD bus.
Table 38.
ISA Cycles (Continued)
Symbol
Parameter Description
Notes
33-MHz
External Bus
Min
Unit
Max
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參數(shù)描述
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