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參數(shù)資料
| 型號(hào)： | EM19110M |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 10-BIT 5 MSPS A/D CONVERTER |
| 中文描述： | 10位5 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 4/6頁 |
| 文件大?。?/td> | 46K |
| 代理商： | EM19110M |
* This specification are subject to be changed without notice.
EM19110
10-BIT 5 MSPS A/D CONVERTER
4
5.26.1997
Application Note
1. AVDD ,DVDD ,VSS
To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and
analog VDD pins, use a ceramic capacitor of about 0.1uF set as close as possible to the pin to bypass to the
respective GND’s.
2. Signal input Vi
Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However
it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When
driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by
inserting a resistance of about 100( in series between the amplifier output and A/D input.
3. Clock input
The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate
it from other circuits.
4. Reference voltage
Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and
VRB pins to GND, by means of a capacitor about 0.1uF, stable characteristics are obtained. By shorting VRT
and VRTS, VRB and VRBS, the self bias function that generates VRT=4.0V and VRB=1.0V, is activated.
Also, the users can setup external reference voltage by just connecting VRT and VRB to desired DC voltage
under spec.
5. Clock timing
Clock
N-3
N-2
N-1
N
N
N+1
N+2
N+3
N+4
N+1
Analog input
Data output
TIMING DIAGRAM
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