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參數(shù)資料
| 型號： | EM39LV80055RH |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | IC, DIGITAL, OCTAL BUS XCEIVER & 3.3V TO 5.0V, SHFTR BIDRCNTL, V XLATOR, 24PIN T |
| 中文描述： | 分位（512Kx16）閃存 |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 295K |
| 代理商： | EM39LV80055RH |
EM39LV800
8M Bits (512Kx16) Flash Memory
SPECIFICATION
This specification is subject to change without further notice. (04.09.2004 V1.0)
Page 16 of
25
Toggle Bit Timing Diagram
T
OES
Two Read Cycles
With Same Outputs
T
CE
T
OE
T
OEH
WE#
OE#
CE#
DQ6
A18~A0
Figure 5:
Toggle Bit Timing Diagram
WE# Controlled Chip-Erase Timing Diagram
Six-Byte Code For Chip-Erase
T
SCE
T
WP
5555
2AAA
5555
5555
2AAA
5555
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
CE#
OE#
WE#
DQ15-0
Note: This device also supports CE# controlled Chip-Erase operation. The WE#and CE#
signals are interchageable as long as minimum timings are met. (See Table 14)
X can be V
IL
or V
IH
, but no other value.
A18~A0
Figure 6:
WE# Controlled Chip-Erase Timing Diagram
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