參數(shù)資料
型號： EM773FHN33,551
廠商： NXP Semiconductors
文件頁數(shù)： 9/51頁
文件大?。?/td> 0K
描述： IC ENERGY METER ARM 32VQFN
其它有關(guān)文件： EM773 Energy Metering IC Training
特色產(chǎn)品： EM773 Energy Metering IC
標(biāo)準(zhǔn)包裝： 260
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 48MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，WDT
輸入/輸出數(shù)： 25
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
配用： 568-6681-ND - BOARD EVAL EM773 METER EU PLUG
568-6680-ND - BOARD EVAL EM773 METER US PLUG
其它名稱： 568-5213
EM773
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 3 January 2012
17 of 51
NXP Semiconductors
EM773
Energy metering IC
7.15.5.1
Power profiles
The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
EM773 for one of the following power modes:
Default mode corresponding to power configuration after reset.
CPU performance mode corresponding to optimized processing capability.
Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
7.15.5.2
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.15.5.3
Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut
down. As an exception, the user has the option to keep the watchdog oscillator and the
BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows
for additional power savings.
Up to 13 pins total serve as external wake-up pins to the start logic to wake up the chip
from Deep-sleep mode.
Unless the watchdog oscillator is selected to run in Deep-sleep mode, the clock source
should be switched to IRC before entering Deep-sleep mode, because the IRC can be
switched on and off glitch-free.
7.15.5.4
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The EM773 can wake up from Deep power-down mode via the WAKEUP
pin.
A LOW-going pulse as short as 50 ns wakes up the part from Deep power-down mode.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. The RESET pin must also be held HIGH to prevent it from
floating while in Deep power-down mode.
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