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參數(shù)資料
| 型號(hào)： | EM78P451SP |
| 廠商： | ELAN Microelctronics Corp . |
| 英文描述： | 8-Bit Microcontroller with OTP ROM |
| 中文描述： | 8位微控制器的OTP ROM的 |
| 文件頁(yè)數(shù)： | 14/54頁(yè) |
| 文件大小： | 421K |
| 代理商： | EM78P451SP |
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EM78P451S
8-Bit Microcontroller with OTP ROM
4.1.12 RE (TMR1: Timer1 register)
10
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0X0E
TMR1/RE TMR17
TMR16
TMR15
TMR14
TMR13
TMR12
TMR11 TMR10
TMR17~TMR10
is bit set of timer1 register and it increases until the value matches
PWP and then, it resets to 0.
4.1.13 RF (PWP: Pulse width preset register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0F
PWP/RF
PWP7
PWP6
PWP5
PWP4
PWP3
PWP2
PWP1
PWP0
PWP7~PWP0
is bit set of pulse width preset in advance for the desired width of baud
clock.
4.1.14 R20~R3E (General Purpose Register)
RA~R1F, and R20~R3E (including Banks 0~3)
are general-purpose registers.
4.1.15 R3F (Interrupt Status Register)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x3F
ISR/R3F
-
-
-
-
TM1IF
SPIIF
EXIF
TCIF
Bits 7~4
are not used and read as “0”.
Bit 3 (TM1IF)
Timer1 interrupt flag. Set by the comparator at Timer1 application, flag
cleared by software.
Bit 2 (SPIIF)
SPI interrupt flag. Set by data transmission complete, flag cleared by
software.
Bit 1 (EXIF)
External interrupt flag. Set by falling edge on /INT pin, flag cleared by
software
Bit 0 (TCIF)
the flag of the TCC overflow interrupt. Set as TCC overflow; flag cleared
by software.
"1" means interrupt request, "0" means non-interrupt.
R3F can be cleared by instruction, but cannot be set by instruction.
IOCF is the interrupt mask register.
Note that to read R3F will result to "logic AND" of R3F and IOCF.
4.2 Special Purpose Registers
4.2.1
A (Accumulator)
Internal data transfer, or instruction operand holding.
A non-addressable register.
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