參數(shù)資料
型號: EM78P451SP
廠商: ELAN Microelctronics Corp .
英文描述: 8-Bit Microcontroller with OTP ROM
中文描述: 8位微控制器的OTP ROM的
文件頁數(shù): 24/54頁
文件大小: 421K
代理商: EM78P451SP
EM78P451S
8-Bit Microcontroller with OTP ROM
20
Product Specification (V1.0) 06.01.2004
(This specification is subject to change without further notice)
P92/SDI: Serial Data In.
P93/SDO: Serial Data Out.
P94/SCK: Serial Clock.
P95//SS: Slave Select (Option). This pin (/SS) may be required during a slave
mode.
RBF: Set by Buffer Full Detector, and reset in software.
RBIF: Set by Buffer Full Detector, and reset in software.
Buffer Full Detector: Sets to 1 when an 8-bit shifting is completed.
SSE: Loads the data in SPIS register, and begin to shift
SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIS register
and the SPIW register are loaded at the same time. Once data are written, SPIS
starts transmission / reception. The received data will be moved to the SPIR
register as the shifting of the 8-bit data is completed. The RBF (Read Buffer Full)
flag and the RBFI(Read Buffer Full Interrupt) flag are then set.
SPIR reg.: Read buffer. The buffer will be updated as the 8-bit shifting is
completed. The data must be read before the next reception is completed. The
RBF flag is cleared as the SPIR register reads.
SPIW reg.: Write buffer. The buffer will deny any attempt to write until the 8-bit
shifting is completed.
The SSE bit will be kept in 1 if the communication is still undergoing. This flag must be
cleared as the shifting is completed. Users can determine if the next write attempt is
available.
SBRS2~SBRS0: Programming the clock frequency/rates and sources.
Clock Select:Selecting either the internal or external clock as the shifting clock.
Edge Select: Selecting the appropriate clock edges by programming the CES bit
4.5.3 SPI Signal & Pin Description
The detailed functions of the four pins, SDI, SDO, SCK, and /SS, which are shown in
Fig. 9, are as follows:
SDI/P92 (Pin 7):
Serial Data In,
Receive serially, the Most Significant Bit (MSB) first, Least Significant Bit (LSB)
last,
Defined as high-impedance, if not selected,
Program the same clock rate and clock edge to latch on both the master and slave
devices,
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