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EM78P468N
8-BIT Microcontroller
20
Product Specification (V1.2) 03.15.2005
(This specification is subject to change without further notice)
Bit 7 (IOC67)~Bit 0(IOC60):
PORT 6 I/O direction control register
IOC6x =”0”:
set the relative PORT6.x I/O pins as output
edance (input pin)
4.2.4
C70
ddr
R (
07h
7
0 of
ntr
“0
gis
IOC6x =”1”:
set the relative PORT6.x I/O pin into high imp
IO
(A
/P7C
ess:
Bit 6
PORT
, Bit
Bit 5
I/O Co
R5 =
Bit 4
ol Re
”)
Bit 3
ter)
Bit 7
Bit 2
Bit 1
Bit 0
IOC77
IOC76
IOC75
IOC74
IOC73
IOC72
IOC71
IOC70
Bit 7 (IOC77)~Bit 0(IOC70):
PORT 7 I/O direction control register
IOC7x = “0”:
set the relative PORT7.x I/O pins as output
4.2
)
(Address: 08h, Bit
Bit 7
Bit 6
IOC7x = “1”:
set the relative PORT7.x I/O pin into high impedance (input pin)
.5
IOC80/P8CR (PORT 8 I/O Control Register
0 of R5 = “0”)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IOC
3
IOC82
IOC81
IOC80
87
IOC86
IOC85
IOC84
IOC8
Bit 7 (IOC 87
(IOC 8
PORT 8 I/O dire
0):
ster
IOC8x = “0”:
set the relative PORT8.x I/O pins as output
4.2
)~Bit 0
ction control regi
IOC8x = “1”:
set the relative PORT8.x I/O pin into high impedance (input pin)
.6
IOC90/RAM_ADDR (128 Bytes RAM Address)
(Address: 09h, Bit 0 of R5 = “0”)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
Bit 7:
Not used,
Bit 6~0:
128 bytes RAM address
4.2.7
ata Buffer)
ddr
0Ah
0 o
“0
fixed at “0”
IOCA0/RAM_DB (128 Bytes RAM D
(A
ess:
, Bit
Bit 7
Bit 6
Bit 5
f R5 =
Bit 4
”)
Bit 3
Bit 2
Bit 1
Bit 0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
Bit 7~0:
128 bytes RAM data transfer register
.8
IOCB0/CNT1PR (Counter 1 Preset Register)
(Address: 0Bh, Bit 0 of R5 = “0”)
Bit 7
Bit 6
Bit 5
4.2
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7 ~ Bit 0:
All are Counter 1
8-bit down-count timer with 8-bit pre-scaler that is used as this register to preset the
read and write. The Counter 1 is an
buffer that user can