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EM78P468N
8-BIT Microcontroller
Fig. 14 Circuit 2 for the Residue Voltage Protection
errupt
4.8 Int
T
h-pu
erflow interru
w-pu
erflow interrup
riggered or as follows
:
TCC timer overflow interrupt,
F
8-bits down c
nter/timer underflow interrupt
ou
If these interrupt source
ag to corresponding register if the IOCF0 register is enabled.
fl
e sign
w, the RF register will generate “1”
al from high to lo
flag bit. IOCF0 is the
interrupt mask register. Global interrupt is enabled by ENI instruction and disabled by
DISI instruction. When one of the interrupts (when enabled) is generated, it will cause the
next instruction t
o be fetch from address 0003H~0018H according to interrupt source.
n interrupt vector as depicted in
the contents of ACC and the R3
r the interrupt service routine is completed,
rrupt service routine does not allow other
occur while the existing
g executed, the hardware will save the later in
rrupt serv
is comple
Table 3. Before the interru
regist
ACC
and R3 are restored. The existing inte
interrupt service routine to be executed. So if other interrupts
interrupt service routine is bein
O
t
servi
e is executed
ce routin
terrupts.
g inte
ice routine
ted that the next interrupt
his LSI has eight interrupt sources as listed below:
TCC overflow interrupt.
External interrupt P5.4/INTO pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
Hig
lse width timer und
pt
Lo
lse width timer und
t
Port 6, Port 8 input status change wake-up
This IC has internal interrupts which are falling edge t
our
s chang
RF is the interrupt status register. It records the interrupt request in
With this LSI, each individual interrupt source has its ow
pt subroutine is executed,
er are initially saved by hardware. Afte
nly after he existin
.
Product Specification
(V1.2) 03.15.2005
(This specification is subject to change without further notice)
39