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參數(shù)資料
| 型號： | EM78P5842 |
| 廠商： | ELAN Microelctronics Corp . |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8 BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 18/48頁 |
| 文件大小： | 469K |
| 代理商： | EM78P5842 |
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EM78P5840/5841/5842
8-bit Micro-controller
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to change without notice.
2004/11/10 V2.6
RE (Interrupt flag)
PAGE0 (Interrupt flag)
7
PWM2
R/W-0
Bit0 ~ Bit3, Bit6: These four bits must clear to 0 or unable to expect error will occur .
Bit 4(PWM1) : PWM1 one period reach interrupt flag.
Bit 5 (ADI) : ADC interrupt flag after a sampling
Bit 7 (PWM2) : PWM2 (Pulse Width Modulation channel 2) interrupt flag
Set when a selected period is reached, reset by software.
PAGE2,3
(undefined) not allowed to use.
RF (Interrupt status)
(Interrupt status register)
7
6
5
4
INT3
0
0
INT1
R/W-0
R/W-X
R/W-X
R/W-0
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF) : TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1(CNT1) : counter1 timer overflow interrupt flag
Set when counter1 timer overflows.
Bit 2,5,6: Unused (These bits are not sure to 0 or 1. When programmer determine what interrupt occur in
subroutine, be care to note these bits)
Bit 3(INT0): By setting PORT70 to general IO, INT0 will define to PORT70 pin’s interrupt flag. If PORT70 has
a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit. If setting
the pin to PLLC or OSCI, PORT70 interrupt will un-exist and INT0 register will be ignored.
Bit 4(INT1): By setting PORT71 to general IO, INT1 will define to PORT71 pin’s interrupt flag. External pull
high circuit is needed for PORT71 interrupt operation. If PORT71 has a falling edge trigger signal, CPU
will set this bit. If setting the pin to /RESET, PORT71 interrupt will un-exist and INT1 register will be
ignored.
Bit 7(INT3): External PORT73 pin interrupt flag. If PORT73 has a falling edge trigger signal, CPU will set this
bit.
6
0
5
4
3
0
2
0
1
0
0
0
ADI
R/W-0
PWM1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
3
2
0
1
0
INT0
R/W-0
CNT1
R/W-0
TCIF
R/W-0
R/W-X
<Note> IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Signal
Trigger
TCC
Time out
COUNTER1
Time out
INT0
Falling
Rising edge
INT1
Falling edge
INT3
Falling edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
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